File: mem01.v

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ghdl 5.0.1%2Bdfsg-1
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module mem01(output [0:7] r, input [0:7] v,
             input wen, input[0:3] addr, input clk);
   reg [7:0] mem [0:3];

   always @(posedge clk)
     if (wen)
       mem[addr] <= v;
   
   assign r = mem[addr];
endmodule