File: comp03.vhdl

package info (click to toggle)
ghdl 5.0.1%2Bdfsg-1
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid, trixie
  • size: 86,000 kB
  • sloc: ada: 309,826; vhdl: 209,727; ansic: 31,072; python: 19,213; sh: 14,214; cpp: 2,345; makefile: 1,542; pascal: 585; asm: 45; exp: 40; fortran: 33
file content (13 lines) | stat: -rw-r--r-- 250 bytes parent folder | download | duplicates (3) 
1
2
3
4
5
6
7
8
9
10
11
12
13
 
library ieee;
use ieee.std_logic_1164.all;

entity comp03 is
  port (p : std_logic_vector (6 downto 0);
        o : out std_logic);
end comp03;

architecture behav of comp03 is
begin
  inst: entity work.sub1
    port map (p => p, o => o);
end behav;