File: tb_initial02.v

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ghdl 5.0.1%2Bdfsg-1
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module tb_initial02;
   reg clk, din, en;
   wire dout;

   initial02 dut (.clk (clk), .din (din), .en (en), .dout(dout));

   initial begin
      clk <= 1'b0;
      din <= 1'b1;
      en <= 1'b1;
      #1;
      if (dout !== 1'b0)
	$fatal(1, "FAILURE-1");

      clk <= 1'b1;
      #1;
      if (dout !== 1'b1)
	$fatal(1, "FAILURE-2");

      $display("PASS");
      $finish;
   end
endmodule