File: test_orig.vhdl

package info (click to toggle)
ghdl 5.0.1%2Bdfsg-1
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid, trixie
  • size: 86,000 kB
  • sloc: ada: 309,826; vhdl: 209,727; ansic: 31,072; python: 19,213; sh: 14,214; cpp: 2,345; makefile: 1,542; pascal: 585; asm: 45; exp: 40; fortran: 33
file content (17 lines) | stat: -rw-r--r-- 504 bytes parent folder | download | duplicates (3) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test is
    port(
         addr_in : in std_logic_vector(11 downto 0);
         dat_out : out std_ulogic_vector(63 downto 0)
         );
end entity test;

architecture behaviour of test is
    type ram_t is array(0 to (4096 / 8) - 1) of std_logic_vector(63 downto 0);
    signal memory : ram_t := (others => (others => '0'));
begin
    dat_out <= memory(to_integer(unsigned(addr_in(11 downto 3))));
end architecture behaviour;