File: repro1.vhdl

package info (click to toggle)
ghdl 5.0.1%2Bdfsg-1
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid, trixie
  • size: 86,000 kB
  • sloc: ada: 309,826; vhdl: 209,727; ansic: 31,072; python: 19,213; sh: 14,214; cpp: 2,345; makefile: 1,542; pascal: 585; asm: 45; exp: 40; fortran: 33
file content (26 lines) | stat: -rw-r--r-- 477 bytes parent folder | download | duplicates (3) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
 
library ieee;
use ieee.std_logic_1164.all;

entity repro1 is
	port (
		Clock   : in std_ulogic;
		Reset   : in std_ulogic;
		Sig_in  : in std_ulogic;
		Sig_out : out std_ulogic
	);
end entity;

architecture rtl of repro1 is
begin
  reg: process(Clock, Reset)
    variable pl_regs : std_ulogic;
  begin
    if Reset = '1' then
      pl_regs := '0';
    elsif rising_edge(Clock) then
      pl_regs := Sig_in;
    end if;

    Sig_out <= pl_regs;
  end process;
end architecture;