File: test2.vhdl

package info (click to toggle)
ghdl 5.0.1%2Bdfsg-1
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid, trixie
  • size: 86,000 kB
  • sloc: ada: 309,826; vhdl: 209,727; ansic: 31,072; python: 19,213; sh: 14,214; cpp: 2,345; makefile: 1,542; pascal: 585; asm: 45; exp: 40; fortran: 33
file content (25 lines) | stat: -rw-r--r-- 499 bytes parent folder | download | duplicates (3) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test2 is
    port(
        clk : in std_logic;
        write_data : in std_ulogic;
        rst : std_ulogic
        );
end;

architecture rtl of test2 is
begin
    test_1: process(clk)
    begin
      if rising_edge(clk) then
        if rst = '1' then
          null;
        else
          assert write_data = '0' report "bad" severity failure;
        end if;
      end if;
    end process test_1;
end architecture rtl;