File: testsuite.sh

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ghdl 5.0.1%2Bdfsg-1
  • links: PTS, VCS
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  • in suites: forky, sid, trixie
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  • sloc: ada: 309,826; vhdl: 209,727; ansic: 31,072; python: 19,213; sh: 14,214; cpp: 2,345; makefile: 1,542; pascal: 585; asm: 45; exp: 40; fortran: 33
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#! /bin/sh

. ../../testenv.sh

synth --out=verilog bug.vhdl -e > synth_bug.v
diff_nocr synth_bug.ref synth_bug.v

echo "Test successful"