File: testsuite.sh

package info (click to toggle)
ghdl 5.0.1%2Bdfsg-1
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid, trixie
  • size: 86,000 kB
  • sloc: ada: 309,826; vhdl: 209,727; ansic: 31,072; python: 19,213; sh: 14,214; cpp: 2,345; makefile: 1,542; pascal: 585; asm: 45; exp: 40; fortran: 33
file content (20 lines) | stat: -rwxr-xr-x 389 bytes parent folder | download 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
 
#! /bin/sh

. ../../testenv.sh

synth --out=verilog flip_flop.vhdl -e > syn_flip_flop.v
if grep "input  wire" syn_flip_flop.v; then
  exit 1
fi

synth --out=verilog testcase2.vhdl -e > syn_testcase2.v
if grep "assign edge" syn_testcase2.v; then
  exit 1
fi

synth --out=verilog testcase3.vhdl -e > syn_testcase3.v
if grep "edge =" syn_testcase3.v; then
  exit 1
fi

echo "Test successful"