File: repro.vhdl

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ghdl 5.0.1%2Bdfsg-1
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file content (16 lines) | stat: -rw-r--r-- 259 bytes parent folder | download 
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std_unsigned.all;

entity repro is
   port (
      o : out std_logic_vector(15 downto 0)
   );
end;

architecture behav of repro is
  signal v : natural;
begin
  o <= to_stdlogicvector(v, 16);
end;