File: zybo_top.vhdl

package info (click to toggle)
ghdl 5.0.1%2Bdfsg-1
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid, trixie
  • size: 86,000 kB
  • sloc: ada: 309,826; vhdl: 209,727; ansic: 31,072; python: 19,213; sh: 14,214; cpp: 2,345; makefile: 1,542; pascal: 585; asm: 45; exp: 40; fortran: 33
file content (22 lines) | stat: -rw-r--r-- 457 bytes parent folder | download 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
 


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity zybo_top is
  port(
		signal inA : in  std_logic_vector(24 downto 0);
		signal inB : in  std_logic_vector(17 downto 0);
		signal res : out std_logic_vector(31 downto 0)
	);
end zybo_top;

architecture synth of zybo_top is

begin

	-- Simple functionality : This should fit in 1 DSP48E1
	res <= std_logic_vector(resize(signed(inA) * signed(inB), res'length));

end architecture;