File: ent.vhdl

package info (click to toggle)
ghdl 5.0.1%2Bdfsg-1
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid, trixie
  • size: 86,000 kB
  • sloc: ada: 309,826; vhdl: 209,727; ansic: 31,072; python: 19,213; sh: 14,214; cpp: 2,345; makefile: 1,542; pascal: 585; asm: 45; exp: 40; fortran: 33
file content (22 lines) | stat: -rw-r--r-- 440 bytes parent folder | download | duplicates (3) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
 
library ieee;
use ieee.std_logic_1164.all;

entity ent is
end;

architecture a of ent is
    function count_ones(vec : std_logic_vector) return natural is
        variable temp : natural := 0;
    begin
        for i in vec'range loop
            if vec(i) then
                temp := temp + 1;
            end if;
        end loop;

        return temp;
    end count_ones;

    constant test : natural := count_ones("10101");
begin
end;