File: local-powerpc8xx-dcbz.diff

package info (click to toggle)
glibc 2.24-10
  • links: PTS, VCS
  • area: main
  • in suites: stretch
  • size: 223,412 kB
  • sloc: ansic: 991,967; asm: 261,800; sh: 10,385; makefile: 9,710; cpp: 4,169; python: 3,971; perl: 2,254; awk: 1,753; pascal: 1,521; yacc: 291; sed: 80
file content (62 lines) | stat: -rw-r--r-- 2,453 bytes parent folder | download | duplicates (8)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
--- a/sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c
+++ b/sysdeps/unix/sysv/linux/powerpc/dl-sysdep.c
@@ -25,10 +25,28 @@
 /* Scan the Aux Vector for the "Data Cache Block Size" entry.  If found
    verify that the static extern __cache_line_size is defined by checking
    for not NULL.  If it is defined then assign the cache block size
-   value to __cache_line_size.  */
+   value to __cache_line_size.  This is used by memset to
+   optimize setting to zero.  We have to detect 8xx processors, which
+   have buggy dcbz implementations that cannot report page faults
+   correctly.  That requires reading SPR, which is a privileged
+   operation.  Fortunately 2.2.18 and later emulates PowerPC mfspr
+   reads from the PVR register.   */
+#ifndef __powerpc64__
+ #define DL_PLATFORM_AUXV						      \
+      case AT_DCACHEBSIZE:						      \
+	{								      \
+	  unsigned pvr = 0;						      \
+	  asm ("mfspr %0, 287" : "=r" (pvr));				      \
+	  if ((pvr & 0xffff0000) == 0x00500000)				      \
+	    break;							      \
+	}								      \
+ 	__cache_line_size = av->a_un.a_val;				      \
+ 	break;
+#else
-#define DL_PLATFORM_AUXV						      \
+ #define DL_PLATFORM_AUXV						      \
       case AT_DCACHEBSIZE:						      \
 	__cache_line_size = av->a_un.a_val;				      \
 	break;
+#endif
 
 #include <sysdeps/unix/sysv/linux/dl-sysdep.c>
--- a/sysdeps/unix/sysv/linux/powerpc/libc-start.c
+++ b/sysdeps/unix/sysv/linux/powerpc/libc-start.c
@@ -73,11 +73,25 @@
 
   /* Initialize the __cache_line_size variable from the aux vector.  For the
      static case, we also need _dl_hwcap, _dl_hwcap2 and _dl_platform, so we
-     can call __tcb_parse_hwcap_and_convert_at_platform ().  */
+     can call __tcb_parse_hwcap_and_convert_at_platform ().
+     This is used by memset to optimize setting to zero.  We have to
+     detect 8xx processors, which have buggy dcbz implementations that
+     cannot report page faults correctly.  That requires reading SPR,
+     which is a privileged operation.  Fortunately 2.2.18 and later
+     emulates PowerPC mfspr reads from the PVR register.  */
   for (ElfW (auxv_t) * av = auxvec; av->a_type != AT_NULL; ++av)
     switch (av->a_type)
       {
       case AT_DCACHEBSIZE:
+#ifndef __powerpc64__
+	{
+	  unsigned pvr = 0;
+
+	  asm ("mfspr %0, 287" : "=r" (pvr) :);
+	  if ((pvr & 0xffff0000) == 0x00500000)
+	    break;
+	}
+#endif
 	__cache_line_size = av->a_un.a_val;
 	break;
 #ifndef SHARED