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/* $Id: d_mos.model $ -*- C++ -*-
* Copyright (C) 2001 Albert Davis
* Author: Albert Davis <aldavis@gnu.org>
*
* This file is part of "Gnucap", the Gnu Circuit Analysis Package
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*------------------------------------------------------------------
* data structures and defaults for mos model.
* internal units all mks (meters)
* but some user input parameters are in cm.
*
* netlist syntax:
* device: mxxxx d g s b mname <device args> <model card args>
* model: .model mname NMOS <args>
* or .model mname PMOS <args>
*/
h_headers {
#include "d_diode.h"
}
cc_headers {
#include "u_limit.h"
#include "e_storag.h"
#include "d_mos_base.h"
}
/*--------------------------------------------------------------------------*/
device BUILT_IN_MOS {
parse_name mosfet;
model_type BUILT_IN_MOS_BASE;
id_letter M;
circuit {
sync;
ports {d g s b};
local_nodes {
id short_to=d short_if="!OPT::rstray || s->rd == 0.";
is short_to=s short_if="!OPT::rstray || s->rs == 0.";
}
args db BUILT_IN_DIODE {
area = double(s->ad);
perim = double(c->pd);
is_raw = double(s->idsat);
cj_raw = double(m->cbd);
cjsw_raw = NA;
off = true;
set_modelname(modelname());
attach(model());
}
args sb BUILT_IN_DIODE {
area = double(s->as);
perim = double(c->ps);
is_raw = double(s->issat);
cj_raw = double(m->cbs);
cjsw_raw = NA;
off = true;
set_modelname(modelname());
attach(model());
}
resistor Rs {s is} value="s->rs"
omit="!OPT::rstray || s->rs == 0.";
resistor Rd {d id} value="s->rd"
omit="!OPT::rstray || s->rd == 0.";
diode Ddb {b id} args="db" reverse="m->polarity==pP"
omit="_n[n_b].n_() == _n[n_d].n_() || s->idsat == 0.";
diode Dsb {b is} args="sb" reverse="m->polarity==pP"
omit="_n[n_b].n_() == _n[n_s].n_() || s->issat == 0.";
capacitor Cgs {g is} value="s->cgso" eval=Cgs
omit="!OPT::cstray || _n[n_g].n_() == _n[n_s].n_()";
capacitor Cgd {g id} value="s->cgdo" eval=Cgd
omit="!OPT::cstray || _n[n_g].n_() == _n[n_d].n_()";
capacitor Cgb {g b} value="s->cgbo" eval=Cgb
omit="!OPT::cstray || _n[n_b].n_() == _n[n_g].n_()";
fpoly_cap Cqgs {g is g b is b id b}
state=qgs // qgate, cgs, cggb, cgsb, cgdb
omit="m->cmodel != 0 || !OPT::cstray
|| _n[n_g].n_() == _n[n_is].n_()";
fpoly_cap Cqgd {g id g b id b is b}
state=qgd // qgate, cgs, cggb, cgsb, cgdb
omit="m->cmodel != 0 || !OPT::cstray
|| _n[n_g].n_() == _n[n_id].n_()";
fpoly_cap Cqds {id is g b is b id b}
state=qdrn // qdrn, cds, cdgb, cdsb, cddb
omit="m->cmodel != 0 || !OPT::cstray
|| _n[n_id].n_() == _n[n_is].n_()";
fpoly_cap Cqbs {b is g b is b id b}
state=qbs
omit="m->cmodel != 0 || !OPT::cstray
|| _n[n_b].n_() == _n[n_is].n_()";
fpoly_cap Cqbd {b id g b id b is b}
state=qbd
omit="m->cmodel != 0 || !OPT::cstray
|| _n[n_b].n_() == _n[n_id].n_()";
cpoly_g Ids {id is g is id g
b is id b} state=idsxxx;
cpoly_g Idb {id b id is g is b is}
state=idbxxx
omit="!(m->needs_isub) || _n[n_d].n_() == _n[n_b].n_()";
cpoly_g Isb {is b is id g id b id}
state=isbxxx
omit="!(m->needs_isub) || _n[n_s].n_() == _n[n_b].n_()";
}
tr_probe {
v = "@n_d[V] - @n_s[V]";
vds = "@n_d[V] - @n_s[V]";
vgs = "@n_g[V] - @n_s[V]";
vbs = "@n_b[V] - @n_s[V]";
"vdsi{nt}" = "vds";
"vgsi{nt}" = "vgs";
"vbsi{nt}" = "vbs";
vgd = "@n_g[V] - @n_d[V]";
vbd = "@n_b[V] - @n_d[V]";
vsd = "@n_s[V] - @n_d[V]";
vdm = "(@n_d[V] - @n_s[V] + @n_d[V] - @n_d[V]) / 2.";
vgm = "(@n_g[V] - @n_s[V] + @n_g[V] - @n_d[V]) / 2.";
vbm = "(@n_b[V] - @n_s[V] + @n_b[V] - @n_d[V]) / 2.";
vsm = "(@n_s[V] - @n_s[V] + @n_s[V] - @n_d[V]) / 2.";
vdg = "@n_d[V] - @n_g[V]";
vbg = "@n_b[V] - @n_g[V]";
vsg = "@n_s[V] - @n_g[V]";
vdb = "@n_d[V] - @n_b[V]";
vgb = "@n_g[V] - @n_b[V]";
vsb = "@n_s[V] - @n_b[V]";
vd = "@n_d[V]";
vg = "@n_g[V]";
vb = "@n_b[V]";
vs = "@n_s[V]";
"i{d}" = "(_Rd) ? @Rd[I] : (@Ids[I] - @Cgd[I] - @Ddb[I] * m->polarity)";
is = "(_Rs) ? @Rs[I] : (-@Ids[I] - @Cgs[I] - @Dsb[I] * m->polarity)";
ig = "@Cgs[I] + @Cgd[I] + @Cgb[I]";
ib = "- @Ddb[I] * m->polarity - @Dsb[I] * m->polarity - @Cgb[I]";
ibd = "@Ddb[I]";
ibs = "@Dsb[I]";
"cgso{vl}" = "@Cgs[NV]";
"cgdo{vl}" = "@Cgd[NV]";
"cgbo{vl}" = "@Cgb[NV]";
cgst = "@Cgs[EV]";
cgdt = "@Cgd[EV]";
cgbt = "@Cgb[EV]";
"cgs{m}" = "@Cgs[EV] - @Cgs[NV]";
"cgd{m}" = "@Cgd[EV] - @Cgd[NV]";
"cgb{m}" = "@Cgb[EV] - @Cgb[NV]";
cbd = "@Ddb[Cap]";
cbs = "@Dsb[Cap]";
cgate = "s->cgate";
gm = "(reversed) ? gmr : gmf";
"gmb{s}" = "(reversed) ? gmbr : gmbf";
gbd = "@Ddb[G]";
gbs = "@Dsb[G]";
vth = "von * m->polarity";
ids = "m->polarity * ((reversed) ? -ids : ids)";
"idst{ray}" = "- @Cgd[I] + @Ddb[I] * m->polarity";
p ="@Rs[P] +@Rd[P] +@Ddb[P] +@Dsb[P] +@Cgs[P] +@Cgd[P] +@Cgb[P] +@Ids[P]";
pd="@Rs[PD]+@Rd[PD]+@Ddb[PD]+@Dsb[PD]+@Cgs[PD]+@Cgd[PD]+@Cgb[PD]+@Ids[PD]";
ps="@Rs[PS]+@Rd[PS]+@Ddb[PS]+@Dsb[PS]+@Cgs[PS]+@Cgd[PS]+@Cgb[PS]+@Ids[PS]";
REgion = "static_cast<double>((!cutoff) + (!subthreshold * 2)
+ (saturated * 4) + (sbfwd * 10) + ((vbs > vds) * 20)
+ (punchthru * 40)) * ((reversed)? -1 : 1)";
SUBthreshold = "static_cast<double>(subthreshold)";
CUToff = "static_cast<double>(cutoff)";
SATurated= "static_cast<double>(saturated)";
TRIode = "static_cast<double>(!saturated && !subthreshold)";
SBFwd = "static_cast<double>(sbfwd)";
DBFwd = "static_cast<double>(vbs > vds)";
REVersed = "static_cast<double>(reversed)";
status = "static_cast<double>(converged() * 2)";
}
device {
calculated_parameters {
// ordinary drain current
double ids "" default=0.;
double idsxxx;
double gds "dids/dvds" default=0.;
double gmf "dids/dvgs" default=0.;
double gmr "dids/dvgd" default=0.;
double gmbf "dids/dvbs" default=0.;
double gmbr "dids/dvbd" default=0.;
// drain-bulk
double idb "" default=0.;
double idbxxx "" default=0.;
double gdbdb "placeholder" default=0.;
double gdbds "disub/dvds" default=0.;
double gdbgs "disub/dvgs" default=0.;
double gdbbs "disub/dvbs" default=0.;
// source-bulk
double isb "" default=0.;
double isbxxx "" default=0.;
double gsbsb "placeholder" default=0.;
double gsbsd "disub/dvds" default=0.;
double gsbgd "disub/dvgs" default=0.;
double gsbbd "disub/dvbs" default=0.;
// charge
double qgate "raw" default=0.;
double cgs "dqgate_vgs placeholder" default=0.;
double cggb "dqgate_vgb" default=0.;
double cgsb "dqgate_vsb" default=0.;
double cgdb "dqgate_vdb" default=0.;
double qgs "forward mode" default=0.;
double cgsgs "dqgs_vgs placeholder" default=0.;
double cgsgb "dqgs_vgb" default=0.;
double cgssb "dqgs_vsb" default=0.;
double cgsdb "dqgs_vdb" default=0.;
double qgd "reverse mode" default=0.;
double cgdgd "dqgd_vgs placeholder" default=0.;
double cgdgb "dqgd_vgb" default=0.;
double cgdsb "dqgd_vsb" default=0.;
double cgddb "dqgd_vdb" default=0.;
double qdrn "Qds" default=0.;
double cdsds "dqds_vds placeholder" default=0.;
double cdgb "dqds_vgb" default=0.;
double cdsb "dqds_vsb" default=0.;
double cddb "dqds_vdb" default=0.;
double qbulk "raw" default=0.;
double cbs "dqbs_vbs placeholder" default=0.;
double cbgb "dqbs_vbg" default=0.;
double cbsb "dqbs_vsb" default=0.;
double cbdb "dqbs_vdb" default=0.;
double qbs "Qbs forward" default=0.;
double cbsbs "dqbs_vbs placeholder" default=0.;
double cbsgb "dqbs_vbg" default=0.;
double cbssb "dqbs_vsb" default=0.;
double cbsdb "dqbs_vdb" default=0.;
double qbd "Qbd reverse" default=0.;
double cbdbd "dqbd_vbd placeholder" default=0.;
double cbdgb "dqbd_vbg" default=0.;
double cbdsb "dqbd_vsb" default=0.;
double cbddb "dqbd_vdb" default=0.;
double gtau "" default=0.;
double cqgb "" default=0.;
double cqsb "" default=0.;
double cqdb "" default=0.;
double cqbb "" default=0.;
/*
double tconst "" default=0.;
double cgb "placeholder" default=0.; // capacitors and charges
double qgb "placeholder" default=0.;
double qgd "" default=0.;
double cgd "" default=0.;
double qgs "" default=0.;
//double cgs "" default=0.;
*/
double vgs "terminal voltages" default=0.;
double vds "" default=0.;
double vbs "" default=0.;
double vdsat "saturation voltage" default=0.;
double vgst "vgs - von." default=0.;
double von "actual threshold voltage" default=0.;
bool reversed "flag: Vgs < 0, reverse s & d" default=false;
bool cutoff "flag: in cut off region" default=false;
bool subthreshold "flag: subthreshold region" default=false;
bool saturated "flag: in saturation region" default=false;
bool sbfwd "flag: sb diode fwd biased" default=false;
bool punchthru "flag: punch thru region" default=false;
}
}
common {
raw_parameters {
double l_in "drawn (optical) channel length"
name=L positive default="OPT::defl";
double w_in "channel width (drawn)"
name=W positive default="OPT::defw";
double ad_in "drain area, drawn"
name=AD positive default="OPT::defad"
print_test="has_hard_value(ad_in)";
double as_in "source area, drawn"
name=AS positive default="OPT::defas"
print_test="has_hard_value(as_in)";
double pd "drain perimeter" name=PD positive default=0.0
print_test="has_hard_value(pd)";
double ps "source perimeter" name=PS positive default=0.0
print_test="has_hard_value(ps)";
double nrd "drain # squares" name=NRD positive default=1.0
print_test="has_hard_value(nrd)";
double nrs "source # squares" name=NRS positive default=1.0
print_test="has_hard_value(nrs)";
}
}
tr_eval {
int foo=3;
}
/*--------------------------------------------------------------------*/
eval Cgb {
STORAGE* brh = prechecked_cast<STORAGE*>(d);
assert(brh);
double cap = brh->value();
if (m->cmodel != 0) {
if (p->vgst < - s->phi) { /* accumulation */
cap += s->cgate;
}else if (p->vgst < 0.) { /* depletion */
cap += s->cgate * (-p->vgst) / s->phi;
}else{ /* active, overlap only */
}
}
brh->_y[0].f1 = cap;
if (d->_sim->analysis_is_tran_dynamic()) {
cap = (brh->_y[0].f1 + brh->_y[1].f1) / 2;
brh->_y[0].f0 = (brh->_y[0].x - brh->_y[1].x) * cap + brh->_y[1].f0;
}else{
assert(d->_sim->analysis_is_static() || d->_sim->analysis_is_restore());
brh->_y[0].f0 = brh->_y[0].x * brh->_y[0].f1;
}
trace3(brh->long_label().c_str(), brh->_y[0].x, brh->_y[0].f0, brh->_y[0].f1);
}
/*--------------------------------------------------------------------*/
eval Cgd {
STORAGE* brh = prechecked_cast<STORAGE*>(d);
assert(brh);
double cap = 0;
if (m->cmodel != 0) {
assert(p->vdsat >= 0.);
assert(p->vds >= 0.);
double vbs = (m->cmodel == 3) ? 0. : p->vbs;
double vdbsat = p->vdsat - vbs;
double vdb = p->vds - vbs;
double ddif = 2. * vdbsat - vdb;
if (!p->reversed) { // treat as Cgs
if (p->vgst >= 0.) {
if (p->vdsat > p->vds) { /* linear */
cap = (2./3.) * s->cgate * (1. - (vdbsat*vdbsat)/(ddif*ddif));
if (p->vgst <= .1) {
cap *= 10. * p->vgst; // smooth discontinuity
}
}
}
}else{ // treat as Cgs
if (p->vgst >= -s->phi/2.) { /* depletion or active */
cap = (2./3.) * s->cgate;
if (p->vdsat > p->vds) { /* linear */
double ndif = p->vdsat - p->vds;
cap *= 1. - (ndif*ndif)/(ddif*ddif);
}
if (p->vgst <= 0) {
cap *= 1. + p->vgst / (s->phi);
cap *= 1. + p->vgst / (s->phi);
}
}
}
}
cap += brh->value(); /* else overlap only */
brh->_y[0].f1 = cap;
if (d->_sim->analysis_is_tran_dynamic()) {
cap = (brh->_y[0].f1 + brh->_y[1].f1) / 2;
brh->_y[0].f0 = (brh->_y[0].x - brh->_y[1].x) * cap + brh->_y[1].f0;
}else{
assert(d->_sim->analysis_is_static() || d->_sim->analysis_is_restore());
brh->_y[0].f0 = brh->_y[0].x * brh->_y[0].f1;
}
trace3(brh->long_label().c_str(), brh->_y[0].x, brh->_y[0].f0, brh->_y[0].f1);
}
/*--------------------------------------------------------------------*/
eval Cgs {
STORAGE* brh = prechecked_cast<STORAGE*>(d);
assert(brh);
double cap = 0;
if (m->cmodel != 0) {
assert(p->vdsat >= 0.);
assert(p->vds >= 0.);
double vbs = (m->cmodel == 3) ? 0. : p->vbs;
double vdbsat = p->vdsat - vbs;
double vdb = p->vds - vbs;
double ddif = 2. * vdbsat - vdb;
if (p->reversed) { // treat as Cgd
if (p->vgst >= 0.) {
if (p->vdsat > p->vds) { /* linear */
cap = (2./3.) * s->cgate * (1. - (vdbsat*vdbsat)/(ddif*ddif));
if (p->vgst <= .1) {
cap *= 10. * p->vgst; // smooth discontinuity
}
}
}
}else{ // treat as Cgs
if (p->vgst >= -s->phi/2.) { /* depletion or active */
cap = (2./3.) * s->cgate;
if (p->vdsat > p->vds) { /* linear */
double ndif = p->vdsat - p->vds;
cap *= 1. - (ndif*ndif)/(ddif*ddif);
}
if (p->vgst <= 0) {
cap *= 1. + p->vgst / (s->phi);
cap *= 1. + p->vgst / (s->phi);
}
}
}
}
cap += brh->value(); /* else overlap only */
brh->_y[0].f1 = cap;
if (d->_sim->analysis_is_tran_dynamic()) {
cap = (brh->_y[0].f1 + brh->_y[1].f1) / 2;
brh->_y[0].f0 = (brh->_y[0].x - brh->_y[1].x) * cap + brh->_y[1].f0;
}else{
assert(d->_sim->analysis_is_static() || d->_sim->analysis_is_restore());
brh->_y[0].f0 = brh->_y[0].x * brh->_y[0].f1;
}
trace3(brh->long_label().c_str(), brh->_y[0].x, brh->_y[0].f0, brh->_y[0].f1);
}
/*--------------------------------------------------------------------*/
function reverse_if_needed() {
if (vds < 0) {
error(bTRACE, long_label() + ": reversing\n");
error(bTRACE, "before: vds=%g vgs=%g vbs=%g\n", vds, vgs, vbs);
reversed = !reversed;
vgs -= vds;
vbs -= vds;
vds = -vds;
error(bTRACE, "after: vds=%g vgs=%g vbs=%g\n", vds, vgs, vbs);
if (OPT::dampstrategy & dsREVERSE) {
_sim->_fulldamp = true;
untested();
error(bTRACE, long_label() + ":reverse damp\n");
}
if (!(OPT::mosflags & 0040)) {
vbs = std::min(vbs,0.);
}else{
untested();
}
}
}
/*--------------------------------------------------------------------*/
}
/*--------------------------------------------------------------------------*/
cc_direct {
/*--------------------------------------------------------------------------*/
bool DEV_BUILT_IN_MOS::tr_needs_eval()const
{
if (is_q_for_eval()) {
untested();
return false;
}else if (!converged()) {
return true;
}else{
const COMMON_BUILT_IN_MOS* c = prechecked_cast<const COMMON_BUILT_IN_MOS*>(common());
assert(c);
const MODEL_BUILT_IN_MOS_BASE* m=prechecked_cast<const MODEL_BUILT_IN_MOS_BASE*>(c->model());
assert(m);
polarity_t polarity = m->polarity;
node_t& eff_s((reversed) ? _n[n_id] : _n[n_is]);
node_t& eff_d((reversed) ? _n[n_is] : _n[n_id]);
return !(conchk(vds,polarity*(eff_d.v0()-eff_s.v0()),OPT::vntol)
&& conchk(vgs, polarity*(_n[n_g].v0()-eff_s.v0()),
OPT::vntol)
&& conchk(vbs, polarity*(_n[n_b].v0()-eff_s.v0()),
OPT::vntol));
}
}
/*--------------------------------------------------------------------------*/
bool DEV_BUILT_IN_MOS::do_tr()
{
const COMMON_BUILT_IN_MOS* c = prechecked_cast<const COMMON_BUILT_IN_MOS*>(common());
assert(c);
const MODEL_BUILT_IN_MOS_BASE* m = prechecked_cast<const MODEL_BUILT_IN_MOS_BASE*>(c->model());
assert(m);
bool was_cutoff = cutoff;
bool was_subthreshold = subthreshold;
bool was_saturated = saturated;
bool was_reversed = reversed;
bool was_sbfwd = sbfwd;
polarity_t polarity = m->polarity;
if (_sim->is_initial_step()) {
reversed = false;
vds = vgs = vbs = 0.;
}else{
double Vds, Vgs, Vbs;
if (reversed) {
Vds = polarity * volts_limited(_n[n_is],_n[n_id]);
Vgs = polarity * volts_limited(_n[n_g],_n[n_id]);
Vbs = polarity * volts_limited(_n[n_b],_n[n_id]);
}else{
Vds = polarity * volts_limited(_n[n_id],_n[n_is]);
Vgs = polarity * volts_limited(_n[n_g],_n[n_is]);
Vbs = polarity * volts_limited(_n[n_b],_n[n_is]);
}
vgs = fet_limit_vgs(Vgs, vgs, von);
if (_n[n_d].n_() == _n[n_g].n_()) {
vds = Vds + (vgs - Vgs);
}else{
// Spice hacks Vds here, but my tests show that it often makes
// convergence worse, and never improves it.
// I am guessing that it does help when drain and gate are connected,
// and Spice does it here in case they are and cannot be determined
// whether they are or not.
// The hack maintains Vdg after Vgs limiting.
//Vds = Vds + (vgs - Vgs);
vds = fet_limit_vds(Vds, vds);
}
vbs = std::min(Vbs, 0.);
//vbs = pnj_limit(double Vbs, double vbs, double vt, double vcrit);
//vds = Vds;
//vgs = Vgs;
//vbs = Vbs;
}
assert(qgate == qgate);
assert(qgs == qgs);
assert(qgd == qgd);
assert(qdrn == qdrn);
assert(qbulk == qbulk);
assert(qbs == qbs);
assert(qbd == qbd);
m->tr_eval(this);
assert(qgate == qgate);
assert(qgs == qgs);
assert(qgd == qgd);
assert(qdrn == qdrn);
assert(qbulk == qbulk);
assert(qbs == qbs);
assert(qbd == qbd);
if (reversed) {
idsxxx = ids + vds*gds + vgs*gmr + vbs*gmbr;
isbxxx = isb - vds*gsbsd - vgs*gsbgd - vbs*gsbbd;
idbxxx = 0.;
}else{
idsxxx = ids - vds*gds - vgs*gmf - vbs*gmbf;
idbxxx = idb - vds*gdbds - vgs*gdbgs - vbs*gdbbs;
isbxxx = 0.;
}
ids *= polarity;
idsxxx *= polarity;
assert(subckt());
set_converged(subckt()->do_tr());
trace3(long_label().c_str(), vds, vgs, vbs);
trace4("", ids, gmf, gds, gmbf);
trace4("", ids, gmr, gds, gmbr);
if (was_cutoff != cutoff || was_subthreshold != subthreshold
|| was_saturated != saturated || was_reversed != reversed
|| was_sbfwd != sbfwd) {
if (OPT::dampstrategy & dsDEVREGION) {
_sim->_fulldamp = true;
}else{
}
#if defined(DO_TRACE)
error(bTRACE,"%s: region change\n", long_label().c_str());
#endif
}else{
}
return converged();
}
}
/*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------*/
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