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gplcver 2.12a-1.1
  • links: PTS
  • area: main
  • in suites: bullseye, buster, jessie, jessie-kfreebsd, sid, squeeze, stretch, wheezy
  • size: 7,604 kB
  • ctags: 9,129
  • sloc: ansic: 126,201; sh: 1,539; makefile: 89; perl: 22
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Source: gplcver
Section: devel
Priority: extra
Maintainer: NIIBE Yutaka <gniibe@fsij.org>
Build-Depends: debhelper (>= 5)
Standards-Version: 3.7.2.2

Package: gplcver
Architecture: any
Depends: ${shlibs:Depends}
Description: Verilog simulator
 Cver is a full 1995 IEEE P1364 standard Verilog simulator.  It also
 implements some of the 2001 P1364 standard features.  All three
 PLI interfaces (tf_, acc_, and vpi_) are implemented as defined
 in the IEEE 2001 P1364 LRM.
 .
 Homepage: http://www.pragmatic-c.com/gpl-cver