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gplcver 2.12a-4
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid
  • size: 13,828 kB
  • sloc: ansic: 126,202; sh: 554; makefile: 25; perl: 22
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Source: gplcver
Section: electronics
Priority: optional
Maintainer: Debian Electronics Team <pkg-electronics-devel@lists.alioth.debian.org>
Uploaders: أحمد المحمودي (Ahmed El-Mahmoudy) <aelmahmoudy@users.sourceforge.net>
Build-Depends: debhelper-compat (= 13)
Standards-Version: 4.7.2
Rules-Requires-Root: no
Homepage: https://sourceforge.net/projects/gplcver/
Vcs-Git: https://salsa.debian.org/electronics-team/gplcver.git
Vcs-Browser: https://salsa.debian.org/electronics-team/gplcver

Package: gplcver
Architecture: any
Depends: ${misc:Depends}, ${shlibs:Depends}
Description: Verilog simulator
 Cver is a full 1995 IEEE P1364 standard Verilog simulator.  It also
 implements some of the 2001 P1364 standard features.  All three
 PLI interfaces (tf_, acc_, and vpi_) are implemented as defined
 in the IEEE 2001 P1364 LRM.