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From 264ee53d47f9b9064792aa3d21cff4c54747cf2e Mon Sep 17 00:00:00 2001
From: Jared Boone <jboone@earfeast.com>
Date: Mon, 10 Nov 2014 10:18:56 -0800
Subject: [PATCH 29/68] SPI: Move SCU/pin config to target layers.
---
firmware/common/max2837_target.c | 7 ++++++-
firmware/common/max5864_target.c | 5 +++++
firmware/common/spi_ssp0.c | 25 -------------------------
firmware/common/spi_ssp1.c | 6 ------
firmware/common/w25q80bv_target.c | 22 ++++++++++++++++++++++
5 files changed, 33 insertions(+), 32 deletions(-)
--- a/firmware/common/max2837_target.c
+++ b/firmware/common/max2837_target.c
@@ -28,7 +28,12 @@
void max2837_target_init(max2837_driver_t* const drv) {
(void)drv;
-
+
+ /* Configure SSP1 Peripheral (to be moved later in SSP driver) */
+ scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
+ scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
+ scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
+
scu_pinmux(SCU_XCVR_CS, SCU_GPIO_FAST);
GPIO_SET(PORT_XCVR_CS) = PIN_XCVR_CS;
GPIO_DIR(PORT_XCVR_CS) |= PIN_XCVR_CS;
--- a/firmware/common/max5864_target.c
+++ b/firmware/common/max5864_target.c
@@ -28,6 +28,11 @@
void max5864_target_init(max5864_driver_t* const drv) {
(void)drv;
+ /* Configure SSP1 Peripheral (to be moved later in SSP driver) */
+ scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
+ scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
+ scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
+
/*
* Configure CS_AD pin to keep the MAX5864 SPI disabled while we use the
* SPI bus for the MAX2837. FIXME: this should probably be somewhere else.
--- a/firmware/common/spi_ssp0.c
+++ b/firmware/common/spi_ssp0.c
@@ -23,9 +23,7 @@
#include "spi_ssp0.h"
-#include <libopencm3/lpc43xx/gpio.h>
#include <libopencm3/lpc43xx/rgu.h>
-#include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/ssp.h>
#include "hackrf_core.h"
@@ -47,29 +45,6 @@
SSP_SLAVE_OUT_ENABLE);
spi->config = config;
-
- /* Init SPIFI GPIO to Normal GPIO */
- scu_pinmux(P3_3, (SCU_SSP_IO | SCU_CONF_FUNCTION2)); // P3_3 SPIFI_SCK => SSP0_SCK
- scu_pinmux(P3_4, (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)); // P3_4 SPIFI SPIFI_SIO3 IO3 => GPIO1[14]
- scu_pinmux(P3_5, (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)); // P3_5 SPIFI SPIFI_SIO2 IO2 => GPIO1[15]
- scu_pinmux(P3_6, (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)); // P3_6 SPIFI SPIFI_MISO IO1 => GPIO0[6]
- scu_pinmux(P3_7, (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)); // P3_7 SPIFI SPIFI_MOSI IO0 => GPIO5[10]
- scu_pinmux(P3_8, (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)); // P3_8 SPIFI SPIFI_CS => GPIO5[11]
-
- /* configure SSP pins */
- scu_pinmux(SCU_SSP0_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
- scu_pinmux(SCU_SSP0_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
- scu_pinmux(SCU_SSP0_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION2));
-
- /* configure GPIO pins */
- scu_pinmux(SCU_FLASH_HOLD, SCU_GPIO_FAST);
- scu_pinmux(SCU_FLASH_WP, SCU_GPIO_FAST);
-
- /* drive SSEL, HOLD, and WP pins high */
- gpio_set(PORT_FLASH, (PIN_FLASH_HOLD | PIN_FLASH_WP));
-
- /* Set GPIO pins as outputs. */
- GPIO1_DIR |= (PIN_FLASH_HOLD | PIN_FLASH_WP);
}
void spi_ssp0_transfer_gather(spi_t* const spi, const spi_transfer_t* const transfers, const size_t count) {
--- a/firmware/common/spi_ssp1.c
+++ b/firmware/common/spi_ssp1.c
@@ -21,7 +21,6 @@
#include "spi_ssp1.h"
-#include <libopencm3/lpc43xx/scu.h>
#include <libopencm3/lpc43xx/ssp.h>
#include "hackrf_core.h"
@@ -40,11 +39,6 @@
SSP_SLAVE_OUT_ENABLE);
spi->config = config;
-
- /* Configure SSP1 Peripheral (to be moved later in SSP driver) */
- scu_pinmux(SCU_SSP1_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
- scu_pinmux(SCU_SSP1_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
- scu_pinmux(SCU_SSP1_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION1));
}
void spi_ssp1_transfer_gather(spi_t* const spi, const spi_transfer_t* const transfers, const size_t count) {
--- a/firmware/common/w25q80bv_target.c
+++ b/firmware/common/w25q80bv_target.c
@@ -32,8 +32,30 @@
void w25q80bv_target_init(w25q80bv_driver_t* const drv) {
(void)drv;
+ /* Init SPIFI GPIO to Normal GPIO */
+ scu_pinmux(P3_3, (SCU_SSP_IO | SCU_CONF_FUNCTION2)); // P3_3 SPIFI_SCK => SSP0_SCK
+ scu_pinmux(P3_4, (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)); // P3_4 SPIFI SPIFI_SIO3 IO3 => GPIO1[14]
+ scu_pinmux(P3_5, (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)); // P3_5 SPIFI SPIFI_SIO2 IO2 => GPIO1[15]
+ scu_pinmux(P3_6, (SCU_GPIO_FAST | SCU_CONF_FUNCTION0)); // P3_6 SPIFI SPIFI_MISO IO1 => GPIO0[6]
+ scu_pinmux(P3_7, (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)); // P3_7 SPIFI SPIFI_MOSI IO0 => GPIO5[10]
+ scu_pinmux(P3_8, (SCU_GPIO_FAST | SCU_CONF_FUNCTION4)); // P3_8 SPIFI SPIFI_CS => GPIO5[11]
+
+ /* configure SSP pins */
+ scu_pinmux(SCU_SSP0_MISO, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
+ scu_pinmux(SCU_SSP0_MOSI, (SCU_SSP_IO | SCU_CONF_FUNCTION5));
+ scu_pinmux(SCU_SSP0_SCK, (SCU_SSP_IO | SCU_CONF_FUNCTION2));
+
+ /* configure GPIO pins */
+ scu_pinmux(SCU_FLASH_HOLD, SCU_GPIO_FAST);
+ scu_pinmux(SCU_FLASH_WP, SCU_GPIO_FAST);
scu_pinmux(SCU_SSP0_SSEL, (SCU_GPIO_FAST | SCU_CONF_FUNCTION4));
+
+ /* drive SSEL, HOLD, and WP pins high */
+ gpio_set(PORT_FLASH, (PIN_FLASH_HOLD | PIN_FLASH_WP));
gpio_set(PORT_SSP0_SSEL, PIN_SSP0_SSEL);
+
+ /* Set GPIO pins as outputs. */
+ GPIO1_DIR |= (PIN_FLASH_HOLD | PIN_FLASH_WP);
GPIO5_DIR |= PIN_SSP0_SSEL;
}
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