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CGU_FREQ_MON,0,9,RCNT,9-bit reference clock-counter value,0,rw
CGU_FREQ_MON,9,14,FCNT,14-bit selected clock-counter value,0,r
CGU_FREQ_MON,23,1,MEAS,Measure frequency,0,rw
CGU_FREQ_MON,24,5,CLK_SEL,Clock-source selection for the clock to be measured,0,rw
CGU_XTAL_OSC_CTRL,0,1,ENABLE,Oscillator-pad enable,1,rw
CGU_XTAL_OSC_CTRL,1,1,BYPASS,Configure crystal operation or external-clock input pin XTAL1,0,rw
CGU_XTAL_OSC_CTRL,2,1,HF,Select frequency range,1,rw
CGU_PLL0USB_STAT,0,1,LOCK,PLL0 lock indicator,0,r
CGU_PLL0USB_STAT,1,1,FR,PLL0 free running indicator,0,r
CGU_PLL0USB_CTRL,0,1,PD,PLL0 power down,1,rw
CGU_PLL0USB_CTRL,1,1,BYPASS,Input clock bypass control,1,rw
CGU_PLL0USB_CTRL,2,1,DIRECTI,PLL0 direct input,0,rw
CGU_PLL0USB_CTRL,3,1,DIRECTO,PLL0 direct output,0,rw
CGU_PLL0USB_CTRL,4,1,CLKEN,PLL0 clock enable,0,rw
CGU_PLL0USB_CTRL,6,1,FRM,Free running mode,0,rw
CGU_PLL0USB_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_PLL0USB_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_PLL0USB_MDIV,0,17,MDEC,Decoded M-divider coefficient value,0x5B6A,rw
CGU_PLL0USB_MDIV,17,5,SELP,Bandwidth select P value,0x1C,rw
CGU_PLL0USB_MDIV,22,6,SELI,Bandwidth select I value,0x17,rw
CGU_PLL0USB_MDIV,28,4,SELR,Bandwidth select R value,0x0,rw
CGU_PLL0USB_NP_DIV,0,7,PDEC,Decoded P-divider coefficient value,0x02,rw
CGU_PLL0USB_NP_DIV,12,10,NDEC,Decoded N-divider coefficient value,0xB1,rw
CGU_PLL0AUDIO_STAT,0,1,LOCK,PLL0 lock indicator,0,r
CGU_PLL0AUDIO_STAT,1,1,FR,PLL0 free running indicator,0,r
CGU_PLL0AUDIO_CTRL,0,1,PD,PLL0 power down,1,rw
CGU_PLL0AUDIO_CTRL,1,1,BYPASS,Input clock bypass control,1,rw
CGU_PLL0AUDIO_CTRL,2,1,DIRECTI,PLL0 direct input,0,rw
CGU_PLL0AUDIO_CTRL,3,1,DIRECTO,PLL0 direct output,0,rw
CGU_PLL0AUDIO_CTRL,4,1,CLKEN,PLL0 clock enable,0,rw
CGU_PLL0AUDIO_CTRL,6,1,FRM,Free running mode,0,rw
CGU_PLL0AUDIO_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_PLL0AUDIO_CTRL,12,1,PLLFRACT_REQ,Fractional PLL word write request,0,rw
CGU_PLL0AUDIO_CTRL,13,1,SEL_EXT,Select fractional divider,0,rw
CGU_PLL0AUDIO_CTRL,14,1,MOD_PD,Sigma-Delta modulator power-down,1,rw
CGU_PLL0AUDIO_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_PLL0AUDIO_MDIV,0,17,MDEC,Decoded M-divider coefficient value,0x5B6A,rw
CGU_PLL0AUDIO_NP_DIV,0,7,PDEC,Decoded P-divider coefficient value,0x02,rw
CGU_PLL0AUDIO_NP_DIV,12,10,NDEC,Decoded N-divider coefficient value,0xB1,rw
CGU_PLL0AUDIO_FRAC,0,22,PLLFRACT_CTRL,PLL fractional divider control word,0x00,rw
CGU_PLL1_STAT,0,1,LOCK,PLL1 lock indicator,0,r
CGU_PLL1_CTRL,0,1,PD,PLL1 power down,1,rw
CGU_PLL1_CTRL,1,1,BYPASS,Input clock bypass control,1,rw
CGU_PLL1_CTRL,6,1,FBSEL,PLL feedback select,0,rw
CGU_PLL1_CTRL,7,1,DIRECT,PLL direct CCO output,0,rw
CGU_PLL1_CTRL,8,2,PSEL,Post-divider division ratio P,0x1,rw
CGU_PLL1_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_PLL1_CTRL,12,2,NSEL,Pre-divider division ratio N,0x2,rw
CGU_PLL1_CTRL,16,8,MSEL,Feedback-divider division ratio (M),0x18,rw
CGU_PLL1_CTRL,24,5,CLK_SEL,Clock-source selection,0x01,rw
CGU_IDIVA_CTRL,0,1,PD,Integer divider power down,0,rw
CGU_IDIVA_CTRL,2,2,IDIV,Integer divider A divider value (1/(IDIV + 1)),0x0,rw
CGU_IDIVA_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_IDIVA_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_IDIVB_CTRL,0,1,PD,Integer divider power down,0,rw
CGU_IDIVB_CTRL,2,4,IDIV,Integer divider B divider value (1/(IDIV + 1)),0x0,rw
CGU_IDIVB_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_IDIVB_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_IDIVC_CTRL,0,1,PD,Integer divider power down,0,rw
CGU_IDIVC_CTRL,2,4,IDIV,Integer divider C divider value (1/(IDIV + 1)),0x0,rw
CGU_IDIVC_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_IDIVC_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_IDIVD_CTRL,0,1,PD,Integer divider power down,0,rw
CGU_IDIVD_CTRL,2,4,IDIV,Integer divider D divider value (1/(IDIV + 1)),0x0,rw
CGU_IDIVD_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_IDIVD_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_IDIVE_CTRL,0,1,PD,Integer divider power down,0,rw
CGU_IDIVE_CTRL,2,8,IDIV,Integer divider E divider value (1/(IDIV + 1)),0x00,rw
CGU_IDIVE_CTRL,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_IDIVE_CTRL,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_SAFE_CLK,0,1,PD,Output stage power down,0,r
CGU_BASE_SAFE_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,r
CGU_BASE_SAFE_CLK,24,5,CLK_SEL,Clock source selection,0x01,r
CGU_BASE_USB0_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_USB0_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_USB0_CLK,24,5,CLK_SEL,Clock source selection,0x07,rw
CGU_BASE_PERIPH_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_PERIPH_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_PERIPH_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_USB1_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_USB1_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_USB1_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_M4_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_M4_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_M4_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_SPIFI_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_SPIFI_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_SPIFI_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_SPI_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_SPI_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_SPI_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_PHY_RX_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_PHY_RX_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_PHY_RX_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_PHY_TX_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_PHY_TX_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_PHY_TX_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_APB1_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_APB1_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_APB1_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_APB3_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_APB3_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_APB3_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_LCD_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_LCD_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_LCD_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_VADC_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_VADC_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_VADC_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_SDIO_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_SDIO_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_SDIO_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_SSP0_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_SSP0_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_SSP0_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_SSP1_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_SSP1_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_SSP1_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_UART0_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_UART0_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_UART0_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_UART1_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_UART1_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_UART1_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_UART2_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_UART2_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_UART2_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_UART3_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_UART3_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_UART3_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_OUT_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_OUT_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_OUT_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_AUDIO_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_AUDIO_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_AUDIO_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_CGU_OUT0_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_CGU_OUT0_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_CGU_OUT0_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
CGU_BASE_CGU_OUT1_CLK,0,1,PD,Output stage power down,0,rw
CGU_BASE_CGU_OUT1_CLK,11,1,AUTOBLOCK,Block clock automatically during frequency change,0,rw
CGU_BASE_CGU_OUT1_CLK,24,5,CLK_SEL,Clock source selection,0x01,rw
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