1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
|
I2C0_CONSET,2,1,AA,Assert acknowledge flag,0,rw
I2C0_CONSET,3,1,SI,I2C interrupt flag,0,rw
I2C0_CONSET,4,1,STO,STOP flag,0,rw
I2C0_CONSET,5,1,STA,START flag,0,rw
I2C0_CONSET,6,1,I2EN,I2C interface enable,0,rw
I2C1_CONSET,2,1,AA,Assert acknowledge flag,0,rw
I2C1_CONSET,3,1,SI,I2C interrupt flag,0,rw
I2C1_CONSET,4,1,STO,STOP flag,0,rw
I2C1_CONSET,5,1,STA,START flag,0,rw
I2C1_CONSET,6,1,I2EN,I2C interface enable,0,rw
I2C0_STAT,3,5,STATUS,These bits give the actual status information about the I2C interface,0x1f,r
I2C1_STAT,3,5,STATUS,These bits give the actual status information about the I2C interface,0x1f,r
I2C0_DAT,0,8,DATA,This register holds data values that have been received or are to be transmitted,0,rw
I2C1_DAT,0,8,DATA,This register holds data values that have been received or are to be transmitted,0,rw
I2C0_ADR0,0,1,GC,General Call enable bit,0,rw
I2C0_ADR0,1,7,ADDRESS,The I2C device address for slave mode,0,rw
I2C1_ADR0,0,1,GC,General Call enable bit,0,rw
I2C1_ADR0,1,7,ADDRESS,The I2C device address for slave mode,0,rw
I2C0_SCLH,0,16,SCLH,Count for SCL HIGH time period selection,0x0004,rw
I2C1_SCLH,0,16,SCLH,Count for SCL HIGH time period selection,0x0004,rw
I2C0_SCLL,0,16,SCLL,Count for SCL LOW time period selection,0x0004,rw
I2C1_SCLL,0,16,SCLL,Count for SCL LOW time period selection,0x0004,rw
I2C0_CONCLR,2,1,AAC,Assert acknowledge Clear bit,0,w
I2C0_CONCLR,3,1,SIC,I2C interrupt Clear bit,0,w
I2C0_CONCLR,5,1,STAC,START flag Clear bit,0,w
I2C0_CONCLR,6,1,I2ENC,I2C interface Disable bit,0,w
I2C1_CONCLR,2,1,AAC,Assert acknowledge Clear bit,0,w
I2C1_CONCLR,3,1,SIC,I2C interrupt Clear bit,0,w
I2C1_CONCLR,5,1,STAC,START flag Clear bit,0,w
I2C1_CONCLR,6,1,I2ENC,I2C interface Disable bit,0,w
I2C0_MMCTRL,0,1,MM_ENA,Monitor mode enable,0,rw
I2C0_MMCTRL,1,1,ENA_SCL,SCL output enable,0,rw
I2C0_MMCTRL,2,1,MATCH_ALL,Select interrupt register match,0,rw
I2C1_MMCTRL,0,1,MM_ENA,Monitor mode enable,0,rw
I2C1_MMCTRL,1,1,ENA_SCL,SCL output enable,0,rw
I2C1_MMCTRL,2,1,MATCH_ALL,Select interrupt register match,0,rw
I2C0_ADR1,0,1,GC,General Call enable bit,0,rw
I2C0_ADR1,1,7,ADDRESS,The I2C device address for slave mode,0,rw
I2C1_ADR1,0,1,GC,General Call enable bit,0,rw
I2C1_ADR1,1,7,ADDRESS,The I2C device address for slave mode,0,rw
I2C0_ADR2,0,1,GC,General Call enable bit,0,rw
I2C0_ADR2,1,7,ADDRESS,The I2C device address for slave mode,0,rw
I2C1_ADR2,0,1,GC,General Call enable bit,0,rw
I2C1_ADR2,1,7,ADDRESS,The I2C device address for slave mode,0,rw
I2C0_ADR3,0,1,GC,General Call enable bit,0,rw
I2C0_ADR3,1,7,ADDRESS,The I2C device address for slave mode,0,rw
I2C1_ADR3,0,1,GC,General Call enable bit,0,rw
I2C1_ADR3,1,7,ADDRESS,The I2C device address for slave mode,0,rw
I2C0_DATA_BUFFER,0,8,DATA,This register holds contents of the 8 MSBs of the DAT shift register,0,r
I2C1_DATA_BUFFER,0,8,DATA,This register holds contents of the 8 MSBs of the DAT shift register,0,r
I2C0_MASK0,1,7,MASK,Mask bits,0,rw
I2C1_MASK0,1,7,MASK,Mask bits,0,rw
I2C0_MASK1,1,7,MASK,Mask bits,0,rw
I2C1_MASK1,1,7,MASK,Mask bits,0,rw
I2C0_MASK2,1,7,MASK,Mask bits,0,rw
I2C1_MASK2,1,7,MASK,Mask bits,0,rw
I2C0_MASK3,1,7,MASK,Mask bits,0,rw
I2C1_MASK3,1,7,MASK,Mask bits,0,rw
|
