1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
|
!!omap
- ATIMER_DOWNCOUNTER:
fields: !!omap
- CVAL:
access: rw
description: When equal to zero an interrupt is raised
lsb: 0
reset_value: '0'
width: 16
- ATIMER_PRESET:
fields: !!omap
- PRESETVAL:
access: rw
description: Value loaded in DOWNCOUNTER when DOWNCOUNTER equals zero
lsb: 0
reset_value: '0'
width: 16
- ATIMER_CLR_EN:
fields: !!omap
- CLR_EN:
access: w
description: Writing a 1 to this bit clears the interrupt enable bit in the
ENABLE register
lsb: 0
reset_value: '0'
width: 1
- ATIMER_SET_EN:
fields: !!omap
- SET_EN:
access: w
description: Writing a 1 to this bit sets the interrupt enable bit in the
ENABLE register
lsb: 0
reset_value: '0'
width: 1
- ATIMER_STATUS:
fields: !!omap
- STAT:
access: r
description: A 1 in this bit shows that the STATUS interrupt has been raised
lsb: 0
reset_value: '0'
width: 1
- ATIMER_ENABLE:
fields: !!omap
- ENA:
access: r
description: A 1 in this bit shows that the STATUS interrupt has been enabled
and that the STATUS interrupt request signal is asserted when STAT = 1 in
the STATUS register
lsb: 0
reset_value: '0'
width: 1
- ATIMER_CLR_STAT:
fields: !!omap
- CSTAT:
access: w
description: Writing a 1 to this bit clears the STATUS interrupt bit in the
STATUS register
lsb: 0
reset_value: '0'
width: 1
- ATIMER_SET_STAT:
fields: !!omap
- SSTAT:
access: w
description: Writing a 1 to this bit sets the STATUS interrupt bit in the
STATUS register
lsb: 0
reset_value: '0'
width: 1
|
