1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
|
/*
* Copyright 2025 Great Scott Gadgets <info@greatscottgadgets.com>
*
* This file is part of HackRF.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#include <stdbool.h>
#include "hackrf_core.h"
#include "ice40_spi.h"
#include "fpga.h"
#include "fpga_regs.def"
/* Set up all registers according to the loaded bitstream's defaults. */
void fpga_init(fpga_driver_t* const drv)
{
// Standard bitstream default register values.
set_FPGA_STANDARD_CTRL_DC_BLOCK(drv, true);
set_FPGA_STANDARD_CTRL_QUARTER_SHIFT_EN(drv, false);
set_FPGA_STANDARD_CTRL_QUARTER_SHIFT_UP(drv, false);
set_FPGA_STANDARD_CTRL_PRBS(drv, false);
set_FPGA_STANDARD_CTRL_TRIGGER_EN(drv, false);
set_FPGA_STANDARD_TX_CTRL(drv, 0);
// TODO support the other bitstreams
fpga_regs_commit(drv);
}
void fpga_setup(fpga_driver_t* const drv)
{
// TODO implement fpga_target.c
fpga_init(drv);
}
uint8_t fpga_reg_read(fpga_driver_t* const drv, uint8_t r)
{
uint8_t v;
ssp1_set_mode_ice40();
v = ice40_spi_read(drv->bus, r);
ssp1_set_mode_max283x();
drv->regs[r] = v;
return v;
}
void fpga_reg_write(fpga_driver_t* const drv, uint8_t r, uint8_t v)
{
drv->regs[r] = v;
ssp1_set_mode_ice40();
ice40_spi_write(drv->bus, r, v);
ssp1_set_mode_max283x();
FPGA_REG_SET_CLEAN(drv, r);
}
static inline void fpga_reg_commit(fpga_driver_t* const drv, uint8_t r)
{
fpga_reg_write(drv, r, drv->regs[r]);
}
void fpga_regs_commit(fpga_driver_t* const drv)
{
int r;
for (r = 1; r < FPGA_NUM_REGS; r++) {
if ((drv->regs_dirty >> r) & 0x1) {
fpga_reg_commit(drv, r);
}
}
}
void fpga_set_trigger_enable(fpga_driver_t* const drv, const bool enable)
{
fpga_reg_read(drv, FPGA_STANDARD_CTRL);
set_FPGA_STANDARD_CTRL_TRIGGER_EN(drv, enable & 0b1);
fpga_regs_commit(drv);
}
void fpga_set_rx_dc_block_enable(fpga_driver_t* const drv, const bool enable)
{
set_FPGA_STANDARD_CTRL_DC_BLOCK(drv, enable);
fpga_regs_commit(drv);
}
void fpga_set_rx_decimation_ratio(fpga_driver_t* const drv, const uint8_t value)
{
set_FPGA_STANDARD_RX_DECIM(drv, value & 0b111);
fpga_regs_commit(drv);
}
void fpga_set_rx_quarter_shift_mode(
fpga_driver_t* const drv,
const fpga_quarter_shift_mode_t mode)
{
set_FPGA_STANDARD_CTRL_QUARTER_SHIFT_EN(drv, (mode >> 0) & 0b1);
set_FPGA_STANDARD_CTRL_QUARTER_SHIFT_UP(drv, (mode >> 1) & 0b1);
fpga_regs_commit(drv);
}
void fpga_set_tx_interpolation_ratio(fpga_driver_t* const drv, const uint8_t value)
{
set_FPGA_STANDARD_TX_INTRP(drv, value & 0b111);
fpga_regs_commit(drv);
}
void fpga_set_prbs_enable(fpga_driver_t* const drv, const bool enable)
{
set_FPGA_STANDARD_CTRL(drv, 0);
if (enable) {
set_FPGA_STANDARD_CTRL_PRBS(drv, enable);
}
fpga_regs_commit(drv);
}
void fpga_set_tx_nco_enable(fpga_driver_t* const drv, const bool enable)
{
set_FPGA_STANDARD_TX_CTRL_NCO_EN(drv, enable);
fpga_regs_commit(drv);
}
void fpga_set_tx_nco_pstep(fpga_driver_t* const drv, const uint8_t phase_increment)
{
set_FPGA_STANDARD_TX_PSTEP(drv, phase_increment);
fpga_regs_commit(drv);
}
|
