1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
|
/*
* Copyright (C) 2018-2023 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#include "shared/source/gen8/hw_cmds_base.h"
#include "shared/source/helpers/hw_info.h"
#include "shared/source/helpers/pipe_control_args.h"
#include "shared/source/helpers/pipeline_select_helper.h"
#include "shared/source/helpers/preamble_bdw_and_later.inl"
namespace NEO {
using Family = Gen8Family;
template <>
void PreambleHelper<Family>::addPipeControlBeforeVfeCmd(LinearStream *pCommandStream, const HardwareInfo *hwInfo, EngineGroupType engineGroupType) {
PipeControlArgs args = {};
args.dcFlushEnable = true;
MemorySynchronizationCommands<Family>::addSingleBarrier(*pCommandStream, args);
}
template <>
uint32_t PreambleHelper<Family>::getL3Config(const HardwareInfo &hwInfo, bool useSLM) {
uint32_t l3Config = 0;
switch (hwInfo.platform.eProductFamily) {
case IGFX_BROADWELL:
l3Config = getL3ConfigHelper<IGFX_BROADWELL>(useSLM);
break;
default:
l3Config = getL3ConfigHelper<IGFX_BROADWELL>(true);
}
return l3Config;
}
template <>
void PreambleHelper<Family>::programPipelineSelect(LinearStream *pCommandStream,
const PipelineSelectArgs &pipelineSelectArgs,
const RootDeviceEnvironment &rootDeviceEnvironment) {
using PIPELINE_SELECT = typename Family::PIPELINE_SELECT;
auto pCmd = pCommandStream->getSpaceForCmd<PIPELINE_SELECT>();
PIPELINE_SELECT cmd = Family::cmdInitPipelineSelect;
cmd.setMaskBits(pipelineSelectEnablePipelineSelectMaskBits);
cmd.setPipelineSelection(PIPELINE_SELECT::PIPELINE_SELECTION_GPGPU);
*pCmd = cmd;
}
template <>
size_t PreambleHelper<Family>::getAdditionalCommandsSize(const Device &device) {
bool debuggingEnabled = device.getDebugger() != nullptr;
return getKernelDebuggingCommandsSize(debuggingEnabled);
}
template struct PreambleHelper<Family>;
} // namespace NEO
|
