1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
|
/*
* Copyright (C) 2024 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
#include <cstdint>
#include <string>
namespace NEO {
enum class FaultType : uint16_t {
notPresent = 0b00,
writeAccessViolation = 0b01,
atomicAccessViolation = 0b10
};
enum class FaultAccess : uint16_t {
read = 0b00,
write = 0b01,
atomic = 0b10
};
enum class FaultLevel : uint16_t {
pte = 0b000,
pde = 0b001,
pdp = 0b010,
pml4 = 0b011,
pml5 = 0b0100
};
namespace GpuPageFaultHelpers {
std::string faultTypeToString(FaultType type);
std::string faultAccessToString(FaultAccess access);
std::string faultLevelToString(FaultLevel level);
} // namespace GpuPageFaultHelpers
} // namespace NEO
|
