1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
|
/*
* Copyright (C) 2020-2025 Intel Corporation
*
* SPDX-License-Identifier: MIT
*
*/
#pragma once
namespace NEO {
struct PipeControlArgs {
PipeControlArgs() = default;
void *postSyncCmd = nullptr;
bool blockSettingPostSyncProperties = false;
bool csStallOnly = false;
bool dcFlushEnable = false;
bool renderTargetCacheFlushEnable = false;
bool instructionCacheInvalidateEnable = false;
bool textureCacheInvalidationEnable = false;
bool pipeControlFlushEnable = false;
bool vfCacheInvalidationEnable = false;
bool constantCacheInvalidationEnable = false;
bool stateCacheInvalidationEnable = false;
bool genericMediaStateClear = false;
bool hdcPipelineFlush = false;
bool tlbInvalidation = false;
bool compressionControlSurfaceCcsFlush = false;
bool notifyEnable = false;
bool workloadPartitionOffset = false;
bool amfsFlushEnable = false;
bool unTypedDataPortCacheFlush = false;
bool depthCacheFlushEnable = false;
bool depthStallEnable = false;
bool protectedMemoryDisable = false;
bool isWalkerWithProfilingEnqueued = false;
bool commandCacheInvalidateEnable = false;
};
} // namespace NEO
|
