1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
|
// SPDX-License-Identifier: MIT
/*
* Copyright 2023 Advanced Micro Devices, Inc.
*/
#include <stdio.h>
#include <amdgpu.h>
#include <amdgpu_drm.h>
#include "igt.h"
#include "lib/amdgpu/amd_memory.h"
#define BUFFER_SIZE (4*1024)
#define BUFFER_ALIGN (4*1024)
struct bo_data {
amdgpu_bo_handle buffer_handle;
uint64_t virtual_mc_base_address;
amdgpu_va_handle va_handle;
};
static int
amdgpu_bo_init(amdgpu_device_handle device_handle, struct bo_data *bo)
{
struct amdgpu_bo_alloc_request req = {0};
int r;
req.alloc_size = BUFFER_SIZE;
req.phys_alignment = BUFFER_ALIGN;
req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
r = amdgpu_bo_alloc(device_handle, &req, &bo->buffer_handle);
if (r)
return r;
r = amdgpu_va_range_alloc(device_handle,
amdgpu_gpu_va_range_general,
BUFFER_SIZE, BUFFER_ALIGN, 0,
&bo->virtual_mc_base_address, &bo->va_handle, 0);
if (r)
goto error_va_alloc;
r = amdgpu_bo_va_op(bo->buffer_handle, 0, BUFFER_SIZE,
bo->virtual_mc_base_address, 0, AMDGPU_VA_OP_MAP);
if (r)
goto error_va_map;
return r;
error_va_map:
amdgpu_va_range_free(bo->va_handle);
error_va_alloc:
amdgpu_bo_free(bo->buffer_handle);
return r;
}
static void
amdgpu_bo_clean(amdgpu_device_handle device_handle, struct bo_data *bo)
{
int r;
r = amdgpu_bo_va_op(bo->buffer_handle, 0, BUFFER_SIZE,
bo->virtual_mc_base_address, 0,
AMDGPU_VA_OP_UNMAP);
igt_assert_eq(r, 0);
r = amdgpu_va_range_free(bo->va_handle);
igt_assert_eq(r, 0);
r = amdgpu_bo_free(bo->buffer_handle);
igt_assert_eq(r, 0);
}
static void
amdgpu_bo_export_import_do_type(amdgpu_device_handle device_handle,
struct bo_data *bo, enum amdgpu_bo_handle_type type)
{
struct amdgpu_bo_import_result res = {0};
uint32_t shared_handle;
int r;
r = amdgpu_bo_export(bo->buffer_handle, type, &shared_handle);
igt_assert_eq(r, 0);
r = amdgpu_bo_import(device_handle, type, shared_handle, &res);
igt_assert_eq(r, 0);
igt_assert(res.buf_handle == bo->buffer_handle);
igt_assert_eq(res.alloc_size, BUFFER_SIZE);
r = amdgpu_bo_free(res.buf_handle);
igt_assert_eq(r, 0);
}
static void
amdgpu_bo_export_import(amdgpu_device_handle device, struct bo_data *bo)
{
amdgpu_bo_export_import_do_type(device, bo,
amdgpu_bo_handle_type_gem_flink_name);
amdgpu_bo_export_import_do_type(device, bo,
amdgpu_bo_handle_type_dma_buf_fd);
}
static void
amdgpu_bo_metadata(amdgpu_device_handle device, struct bo_data *bo)
{
struct amdgpu_bo_metadata meta = {0};
struct amdgpu_bo_info info = {0};
int r;
meta.size_metadata = 4;
meta.umd_metadata[0] = 0xdeadbeef;
r = amdgpu_bo_set_metadata(bo->buffer_handle, &meta);
igt_assert_eq(r, 0);
r = amdgpu_bo_query_info(bo->buffer_handle, &info);
igt_assert_eq(r, 0);
igt_assert_eq(info.metadata.size_metadata, 4);
igt_assert_eq(info.metadata.umd_metadata[0], 0xdeadbeef);
}
static void
amdgpu_bo_map_unmap(amdgpu_device_handle device, struct bo_data *bo)
{
uint32_t *ptr;
int i, r;
r = amdgpu_bo_cpu_map(bo->buffer_handle, (void **)&ptr);
igt_assert_eq(r, 0);
for (i = 0; i < (BUFFER_SIZE / 4); ++i)
ptr[i] = 0xdeadbeef;
r = amdgpu_bo_cpu_unmap(bo->buffer_handle);
igt_assert_eq(r, 0);
}
static void
amdgpu_memory_alloc(amdgpu_device_handle device_handle)
{
amdgpu_bo_handle bo;
amdgpu_va_handle va_handle;
uint64_t bo_mc;
/* Test visible VRAM */
bo = gpu_mem_alloc(device_handle,
4096, 4096,
AMDGPU_GEM_DOMAIN_VRAM,
AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
&bo_mc, &va_handle);
gpu_mem_free(bo, va_handle, bo_mc, 4096);
/* Test invisible VRAM */
bo = gpu_mem_alloc(device_handle,
4096, 4096,
AMDGPU_GEM_DOMAIN_VRAM,
AMDGPU_GEM_CREATE_NO_CPU_ACCESS,
&bo_mc, &va_handle);
gpu_mem_free(bo, va_handle, bo_mc, 4096);
/* Test GART cacheable */
bo = gpu_mem_alloc(device_handle,
4096, 4096,
AMDGPU_GEM_DOMAIN_GTT,
0, &bo_mc, &va_handle);
gpu_mem_free(bo, va_handle, bo_mc, 4096);
/* Test GART USWC */
bo = gpu_mem_alloc(device_handle,
4096, 4096,
AMDGPU_GEM_DOMAIN_GTT,
AMDGPU_GEM_CREATE_CPU_GTT_USWC,
&bo_mc, &va_handle);
gpu_mem_free(bo, va_handle, bo_mc, 4096);
/* Test GDS */
bo = gpu_mem_alloc(device_handle, 1024, 0,
AMDGPU_GEM_DOMAIN_GDS, 0,
&bo_mc, &va_handle);
gpu_mem_free(bo, va_handle, bo_mc, 4096);
/* Test GWS */
bo = gpu_mem_alloc(device_handle, 1, 0,
AMDGPU_GEM_DOMAIN_GWS, 0,
&bo_mc, &va_handle);
gpu_mem_free(bo, va_handle, bo_mc, 4096);
/* Test OA */
bo = gpu_mem_alloc(device_handle, 1, 0,
AMDGPU_GEM_DOMAIN_OA, 0,
&bo_mc, &va_handle);
gpu_mem_free(bo, va_handle, bo_mc, 4096);
}
static void
amdgpu_mem_fail_alloc(amdgpu_device_handle device_handle)
{
int r;
struct amdgpu_bo_alloc_request req = {0};
amdgpu_bo_handle buf_handle;
/* Test impossible mem allocation, 1TB */
req.alloc_size = 0xE8D4A51000;
req.phys_alignment = 4096;
req.preferred_heap = AMDGPU_GEM_DOMAIN_VRAM;
req.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
igt_assert_eq(r, -ENOMEM);
if (!r) {
r = amdgpu_bo_free(buf_handle);
igt_assert_eq(r, 0);
}
}
static void
amdgpu_bo_find_by_cpu_mapping(amdgpu_device_handle device_handle)
{
amdgpu_bo_handle bo_handle, find_bo_handle;
amdgpu_va_handle va_handle;
void *bo_cpu;
uint64_t bo_mc_address;
uint64_t offset;
int r;
r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096,
AMDGPU_GEM_DOMAIN_GTT, 0,
&bo_handle, &bo_cpu,
&bo_mc_address, &va_handle);
igt_assert_eq(r, 0);
r = amdgpu_find_bo_by_cpu_mapping(device_handle,
bo_cpu,
4096,
&find_bo_handle,
&offset);
igt_assert_eq(r, 0);
igt_assert_eq(offset, 0);
amdgpu_bo_unmap_and_free(bo_handle, va_handle,
bo_mc_address, 4096);
}
igt_main
{
amdgpu_device_handle device;
struct bo_data bo;
int fd = -1;
igt_fixture {
uint32_t major, minor;
int err;
fd = drm_open_driver(DRIVER_AMDGPU);
err = amdgpu_device_initialize(fd, &major, &minor, &device);
igt_require(err == 0);
igt_info("Initialized amdgpu, driver version %d.%d\n",
major, minor);
err = amdgpu_bo_init(device, &bo);
igt_require(err == 0);
}
igt_subtest("amdgpu_bo_export_import")
amdgpu_bo_export_import(device, &bo);
igt_subtest("amdgpu_bo_metadata")
amdgpu_bo_metadata(device, &bo);
igt_subtest("amdgpu_bo_map_unmap")
amdgpu_bo_map_unmap(device, &bo);
igt_subtest("amdgpu_memory_alloc")
amdgpu_memory_alloc(device);
igt_subtest("amdgpu_mem_fail_alloc")
amdgpu_mem_fail_alloc(device);
igt_subtest("amdgpu_bo_find_by_cpu_mapping")
amdgpu_bo_find_by_cpu_mapping(device);
igt_fixture {
amdgpu_bo_clean(device, &bo);
amdgpu_device_deinitialize(device);
close(fd);
}
}
|
