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// SPDX-License-Identifier: MIT
/*
* Copyright 2025 Advanced Micro Devices, Inc.
*/
#include "lib/amdgpu/amd_memory.h"
#include "lib/amdgpu/amd_sdma.h"
#include "lib/amdgpu/amd_PM4.h"
#include "lib/amdgpu/amd_command_submission.h"
static void
amdgpu_ce_write_after_fence(amdgpu_device_handle device_handle)
{
int r;
amdgpu_context_handle context_handle;
r = amdgpu_cs_ctx_create(device_handle, &context_handle);
igt_assert_eq(r, 0);
amdgpu_command_ce_write_fence(device_handle, context_handle);
amdgpu_cs_ctx_free(context_handle);
}
igt_main
{
amdgpu_device_handle device;
struct amdgpu_gpu_info gpu_info = {0};
int fd = -1;
int r;
bool arr_cap[AMD_IP_MAX] = {0};
igt_fixture {
uint32_t major, minor;
int err;
fd = drm_open_driver(DRIVER_AMDGPU);
err = amdgpu_device_initialize(fd, &major, &minor, &device);
igt_require(err == 0);
igt_info("Initialized amdgpu, driver version %d.%d\n",
major, minor);
r = amdgpu_query_gpu_info(device, &gpu_info);
igt_assert_eq(r, 0);
r = setup_amdgpu_ip_blocks(major, minor, &gpu_info, device);
igt_assert_eq(r, 0);
asic_rings_readness(device, 1, arr_cap);
}
igt_describe("CE memory write visibility after fence");
igt_subtest_with_dynamic("command_ce_write_fence") {
if (arr_cap[AMD_IP_GFX]) {
igt_dynamic_f("ce_write_fence")
amdgpu_ce_write_after_fence(device);
}
}
igt_fixture {
amdgpu_device_deinitialize(device);
drm_close_driver(fd);
}
}
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