1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
|
/*========================== begin_copyright_notice ============================
Copyright (C) 2017-2021 Intel Corporation
SPDX-License-Identifier: MIT
============================= end_copyright_notice ===========================*/
#include "../include/BiF_Definitions.cl"
#include "../../Headers/spirv.h"
#include "../IMF/FP32/log2_s_la.cl"
#if defined(cl_khr_fp64)
#include "../IMF/FP64/log2_d_la.cl"
#include "../IMF/FP64/log2_d_la_noLUT.cl"
#endif // defined(cl_khr_fp64)
INLINE float SPIRV_OVERLOADABLE SPIRV_OCL_BUILTIN(log2, _f32, )( float x )
{
float result;
if(__FastRelaxedMath)
{
result = SPIRV_OCL_BUILTIN(native_log2, _f32, )(x);
}
else
{
result = __ocl_svml_log2f(x);
}
return result;
}
GENERATE_SPIRV_OCL_VECTOR_FUNCTIONS_1ARG_LOOP( log2, float, float, f32 )
#if defined(cl_khr_fp64)
#define _M_LOG2_E_DBL (as_double(0x3ff71547652b82fe)) // 1.4426950408889634073599246
INLINE double SPIRV_OVERLOADABLE SPIRV_OCL_BUILTIN(log2, _f64, )( double x )
{
double result;
if (__UseHighAccuracyMath) {
result = __ocl_svml_log2_noLUT(x);
} else {
result = __ocl_svml_log2_v2(x);
}
return result;
}
GENERATE_SPIRV_OCL_VECTOR_FUNCTIONS_1ARG_LOOP( log2, double, double, f64 )
#endif // defined(cl_khr_fp64)
#if defined(cl_khr_fp16)
INLINE half SPIRV_OVERLOADABLE SPIRV_OCL_BUILTIN(log2, _f16, )( half x )
{
return SPIRV_OCL_BUILTIN(log2, _f32, )((float)x);
}
GENERATE_SPIRV_OCL_VECTOR_FUNCTIONS_1ARG_LOOP( log2, half, half, f16 )
#endif // defined(cl_khr_fp16)
|