1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87
|
/*========================== begin_copyright_notice ============================
Copyright (C) 2021 Intel Corporation
SPDX-License-Identifier: MIT
============================= end_copyright_notice ===========================*/
syntax = "proto3";
import "Metrics/proto_schema/code_reference.proto";
package IGC_METRICS;
message VarInfo {
enum VarType {
Type_UD = 0; // unsigned double word integer
Type_D = 1; // signed double word integer
Type_UW = 2; // unsigned word integer
Type_W = 3; // signed word integer
Type_UB = 4; // unsigned byte integer
Type_B = 5; // signed byte integer
Type_DF = 6;
Type_F = 7; // signed single precision
Type_V = 8; // 32-bit halfbyte integer Vector
Type_VF = 9; // 32-bit restricted Vector Float
Type_BOOL = 10;
Type_UQ = 11; // 64-bit unsigned integer
Type_UV = 12;
Type_Q = 13; // 64-bit signed integer
Type_HF = 14; // half float
Type_BF = 15; // bfloat16 (used in mov only)
Type_UNDEF = 16;
}
enum AddressModel {
GLOBAL = 0;
LOCAL = 1;
}
enum MemAccess {
NONE = 0;
BLOCKED = 1;
STATEFUL = 2;
STATELESS = 3;
ATOMIC = 4;
}
enum PrivArr2Reg
{
Promotable = 0;
IsDynamicAlloca = 1;
CannotUseSOALayout = 2;
IsNotNativeType = 3;
OutOfAllocSizeLimit = 4;
OutOfMaxGRFPressure = 5;
}
message RegUsage {
AddressModel addrModel = 2;
MemAccess memoryAccess = 3;
bool isSpill = 4;
bool isUniform = 5;
bool isConst = 6;
int32 liveRangeStart = 7;
int32 liveRangeEnd = 8;
}
message BankConflictInfo {
int32 count = 1;
int32 sameBank = 2;
int32 twoSrc = 3;
}
optional string name = 1;
int32 size = 2;
VarType type = 3;
repeated RegUsage reg = 4;
BankConflictInfo bc_stats = 5;
optional PrivArr2Reg status_privarr2reg = 6;
optional CodeRef varLoc = 7;
}
|