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|
<!---======================= begin_copyright_notice ============================
Copyright (C) 2020-2021 Intel Corporation
SPDX-License-Identifier: MIT
============================= end_copyright_notice ==========================-->
# vISA Assembly Syntax
Notation
--------
- Left associated rules are used
- \| : indicates "or"
- <abc> : means abc is none-terminal token
- [xyz] : 0 or 1 occurrence of xyz
- [xyz]?: 1 occurrence of x, or y, or z
- [xyz]\* : 0 or more occurrences of x, y and z.
- [xyz]+ : 1 or more occurrences of x, y and z.
- ^ : start position of a line
Lexemes
-------
### Operators:
<operators>::=+\|-\|\*\|/
<assign_operator>::='='
<colon>::=':'
<other_operators>::=, \| ; \| '<' \| '>' \| '(' \| ')'
### Types:
<variable_type> ::= G\|A\|P\|S\|T
<data_type> ::= <FLOAT> \| <INT> \| <BOOLEAN> \| <VECTOR>
<FLOAT>::=f \| df \| F \| DF
<INT>::= ud \| d \| uw \| w \| ub \| b \| UD \| D \| UW \| W \| UB \| B
<BOOLEAN>::=bool \| BOOL
<VECTOR>::= v \| vf \| V \| VF
<src_modifier>::=[(-) \| (abs) \| (-abs)]
### Tokens:
<directives>::=.attr \| .decl \| .input \| .kernel \| .function \|
.version
<pred_ctrl>::= all \| any
<pred_state>::= !
<vme_op_type>::=inter \| intra \| all
<align>::= byte\|word\|dword\|qword\|oword\|GRF\|2GRF
<rel_op>::= eq\|ne\|gt\|ge\|lt\|le\|EQ\|NE\|GT\|GE\|LT\|LE
<start_offset>::=M0\|M1\|M2\|M3\|M4\|M5\|M6\|M7\|NM
<attribute>::= asmName \| FlagRegNum
<other_tokens>::= num_elts \| align \| alias \| type \| v_type \|
size \| attr \| offset \| .sat
<OP>::=
and\|or\|xor\|shl\|shr\|asr\|not\|inv\|log\|exp\|sqrt\|rsqrt\|sin\|cos\|div\|mod\|pow\|frc\|lzd\|rndd\|rndu
\|rnde\|rndz\|add\|avg\|dp2\|dp3\|dp4\|dhp\|line\|mul\|pow\|mulh\|sad2\|mad\|asin\|acos\|atan\|addr_add\|sel\|mov\|movs\|setp\|cmp\|oword_ld\|oword_st\|oword_ld_unaligned\|media_ld\|media_st\|gather\|scatter\|dword_atomic\|sample\|load\|sample_unorm\|vme\|jmp\|call\|ret\|if\|while\|else\|do\|endif\|break\|cont\|vme_fbr\|vme_sic\|vme_ime
<atomic_op>::=add\|sub\|inc\|dec\|min\|max\|xchg\|cmpxchg\|and\|or\|xor\|imin\|imax
### Numbers:
<number>::=<int_number>\|<hex_number>\|<float_point_number>
<int_number>::=<oct_number>\|<hex_number>
<oct_number>::= [0-9]+
<hex_number>::=0x[0-9a-fA-F]+
<float_point_number>::=<float_number_basic>
\|<float_number_science>
< float_number_basic >::=[0-9]+"."[0-9]+
< float_number_science >::= ([0-9]+"."[0-9]+)"e"("+"\|"-")[0-9]+
<exp>::=<INT_NUMBER>\|Exp'+'Exp\|Exp'-'Exp\|Exp'\*'Exp\|Exp'/'Exp\|'-'
Exp\|'('Exp')'
<offset>::=<exp>
### Strings:
<label>::= ^[a-zA-Z_$@?]?[a-zA-Z0-9_\\-$@?]\*
<asmFileName>::=[a-zA-Z_]?[a-zA-Z0-9_\\-$]\*"."asm
<func_name>::=[a-zA-Z_$@\\?]?[a-zA-Z0-9_\\-$@\\?]\*
<bracket_pairs>::= '<'[a-zA-Z_]?[a-zA-Z0-9_\\-, \\t]\*'>' \| '('
[a-zA-Z][a-zA-Z0-9_\\-, \\t]\*')'
<kernel_name>::= [a-zA-Z_]?[a-zA-Z0-9_\\-]\*[<bracket_pairs>]
<var_name>::= [a-zA-Z_]?[a-zA-Z0-9_\\-]\*
<comment>::= /\* <string_with_no_end_comment> \*/
<end_of_line>::='\\n'
vISA Assembly File
------------------
<vISA_Assembly_File>::=<directives_declares> [<kernel_function>]+
<directives_declares>::= <directive_kernel><end_line>
<directive_version><end_line> <directives_declares ><end_line>[
<directives_input ><end_line>]+ [<directives_attr >><end_line>]+
<kernel_function>::=<directive_function>[[<vISA_instructions><end_line>]\|[<decl_label><end_line>]]+
Directives and Declarations Syntax
----------------------------------
### Directives
| Directive | Mnemonic / Syntax | Example |
| --- | --- | --- |
| <directive_attr> | .attr <attr_name>=<attr_value> | .attr AsmName=IS_genx_1.asm |
| <directive_decl> | See following Declarations table | See following Declarations table |
| <directive_input> | .input <input_var> offset=<offset> size=<size> | .input T5 offset=36 size=4 |
| <directive_version> | .version <major_version>.<minor_version> | .version 1.0 |
| <directive_kernel> | .kernel <kernel_name> | .kernel BlockMotionSearch |
| <directive_function> | .function <func_name> | .function foo |
<directive_decl>::=[<decl_gen_var>\|<decl_add_var>\|<decl_pred_var>\|<decl_samp_var>\|<decl_surf_var>]+
### Declarations
| Variable | Declaration Mnemonic / Syntax | Type | Max Count | R\\W | Input | Address-able | Example |
| --- | --- | --- | --- | --- | --- | --- | --- |
| <decl_gen_var> | .decl <gen_var_name> v_type=G type= <data_type> num_elts =<num_elements> [align=<align>] [alias (<alias_variable_name>, <offset>)] | UD, D, UW, W, UB, B, DF, F | 65536 | R\\W | Y | Y | .decl V8 v_type=G type=UD num_elts=1 align=dword |
| <decl_add_var> | .decl <addr_var_name> v_type=A type=<data_type> num_elts=<num_elements> | UW | 4096 | R\\W | N | N | .decl A14 v_type=A type=UW num_elts=1 |
| <decl_pred_var> | .decl <pred_var_name> v_type=P num_elts=<num_elements> [ attr: FlagRegNum =<reg_num>] | BOOL | 4096 | R\\W | N | N | .decl P182 v_type=P num_elts=8 |
| <decl_samp_var> | .decl <samp_var_name> v_type = S | | 16 | R | Y | N | .decl S0 v_type=S |
| <decl_surf_var> | .decl <surf_var_name> v_type=T | | 128 | R | Y | N | .decl T5 v_type=T |
| <decl_label> | <label >: | | 4096 | R | N | N | BB_11224: |
| | | | | | | | ??$d_transpose@M$07$0IA@@@YAXVSurfaceIndex@@0HH@Z: |
<gen_var_name>::=<var_name>
<addr_var_name>::=<var_name>
<pred_var_name>::=<var_name>
<samp_var_name>::=<var_name>
<surf_var_name>::=<var_name>
<input_var>::=<gen_var_name>\|<samp_var_name>\|<surf_var_name>\|<samp_var_name
vISA instruction syntax
-----------------------
### Operands
| Operand position | Operand group | Operand type | Operand type ID | Mnemonic / Syntax | Example |
| --- | --- | --- | --- | --- | --- |
| Execution size | | | <exec_size> | ( <start_offset>, <exp>) | (M1, 4) |
| Predicate | | Predicate | P | [!] <pred_var_name>[.<pred_ctrl>] | !P64.all |
| Source | V_OPND | General | G | [<src_modifier>] <gen_var_name> (<row_offset>, < col_offset>) '<'<vertical_stride>; <width>, <horizontal_stride>'>' | V58(0,0)<8;8,1> |
| Address | A | <addr_var_name> (<offset>)'<'<width>'>' | A3(0)<1> | | |
| Indirect | I | [<src_modifier>]r'[' <addr_var_name>(<addr_offset>), < indirect_offset> ']' '<' <vertical_stride>; <width>, <horizontal_stride>'>': <data_type> | r[A3(0),448]<8;8,1>:ud | | |
| Predicate | P | [<src_modifier>] <pred_var_name> | P17 | | |
| Immediate | IM | <value>:<data_type> | 0x100:uw | | |
| Address Of | AO | &<gen_var_name> [+\|-] <addr_offset> | &V21+0 | | |
| R_OPND | Raw | G | <gen_var_name>.<offset> | V16.0 | |
| OTHERS | Sampler | S | <samp_var_name> | S9 | |
| Surface | T | <surf_var_name> | T2 | | |
| Destination | V_OPND | General | G | <gen_var_name>(<row_offset>, <col_offset>)'<'<horizontal_stride> '>' | V55(0,0)<1> |
| Address | A | <addr_var_name> (<offset>) | A11(0) | | |
| Predicate | P | pred_var_name | P8 | | |
| Indirect | I | r'['< addr_var_name>(<addr_offset>), < indirect_offset> ']' ' <'< horizontal_stride> '>': <data_type> | r[A11(0),64]<1>:ud | | |
| R_OPND | Raw | G | <gen_var_name>.<offset> | V16.0 | |
<horizontal_stride>::= <exp>
< vertical_stride >::= <exp>
<row_offset>::= <exp>
<col_offset>::= <exp>
< addr_offset >::= <exp>
### Instructions formats summary
| Format ID | Mnemonic/Syntax | Operands | Instructions |
| --- | --- | --- | --- |
| 1 | [(P)] <OP> <exec_size> <dst> <src0> | Dst (V_OPND): G\|I | EXP, FRC, LOG, RNDD, RNDU, RNDE, RNDZ, SIN, COS, SQRT, RSQRT, INV, ASIN, ACOS, ATAN, LZD, |
| | | Src0 (V_OPND): G\|I\|IM | |
| Dst (V_OPND): G\|I\|A | MOV | | |
| Src0 (V_OPND): G\|I\|IM\|P \|AO | | | |
| 2 | <OP> <exec_size> <dst> <src0> | Dst (V_OPND): P | STEP, MOVS |
| | | Src0 (V_OPND): G\|I\|IM | |
| 3 | [(P)] <OP> <exec_size> <dst> <src0> <src1> | Dst (V_OPND): G\|I | ADD, AVG, DIV, DP2, DP3, DP4, DPH, MULH, MOD, MUL, SHL, SHR, SEL |
| | | Src0 (V_OPND): G\|I\|IM | |
| | | Src1 (V_OPND): G\|I\|IM | |
| Dst (V_OPND): G\|I | POW, | | |
| Src0 (V_OPND): G\|I\|IM | | | |
| Src1 (V_OPND): G\|I | | | |
| Dst (V_OPND):G\|I\|P | AND, OR, XOR, NOT, | | |
| Src0 (V_OPND):G\|I\|P\|IM | | | |
| Src1 (V_OPND):G\|I\|P\|IM | | | |
| Dst (V_OPND): G\|I | LINE | | |
| Src0 (V_OPND): G | | | |
| Src1 (V_OPND): G\|I\|IM | | | |
| 4 | <OP> <exec_size> <dst> <src0> <src1> | Dst (V_OPND): A | ADDR_ADD |
| | | Src0 (V_OPND):A\|AO | |
| | | Src1 (V_OPND):G\|IM | |
| 5 | [(P)] <OP> <exec_size> <dst> <src0> <src1> <src2> | Dst (V_OPND): G\|I | MAD, |
| | | Src0 (V_OPND): G\|I\|IM | |
| | | Src1 (V_OPND): G\|I\|IM | |
| | | Src2(V_OPND): G\|I\|IM | |
| 6 | CMP.<rel_op> (exec_size) <dst> <src0> <src1> | | Rel_op(ub): EQ\|NE\| GT\| | CMP |
| | | | GE\|LT\|LE | |
| | | | |
| | | | Dst (V_OPND): P | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| | | | Src1 (V_OPND): G\|I\|IM | |
| 7 | [(P)] <OP> (<exec_size>) | | RET |
| 8 | [(P)] <OP> <exec_size> <label> | | JMP, CALL, |
| 9 | <OP> (<start_offset>, <exec_size>) | | ELSE, ENDIF, DO |
| 10 | [(P)]<OP> (<start_offset>, <exec_size>) | | IF, WHILE, BREAK, CONT |
| 11 | Instruction specific syntax | Instruction specific | OWORD_LD, OWORD_ST, MEDIA_LD, MEDIA_ST, GATHER, SCATTER, DWORD_ATOMIC, OWORD_LD_UNALIGNED, SAMPLE, SAMPLE_UNORM, LOAD, FILE, LOC, VME_IME, VME_SIC |
### Instruction syntax
| **ID** | **Opcode** | **Mnemonic / Syntax** | **Operands** |**Data types and other constraints** |
| --- | --- | --- | --- | --- |
| 0 | 0x0 | Reserved | | |
| 1 | 0x1 | [(P)] ADD [.sat] <exec_size> <dst> <src0> <src1> | Exec_size (ub): NO LIMIT | |
| | | | | |
| | | | Dst (V_OPND): G\|I | - Types: FLOAT|INT |
| | | | | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| | | | | |
| | | | Src1 (V_OPND): G\|I\|IM | |
| 2 | 0x2 | [(P)] AVG [.sat] <exec_size> <dst> <src0> <src1> | Exec_size (ub): NO LIMIT | - Type: INT |
| | | | Dst (V_OPND): G\|I | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| | | | Src1 (V_OPND): G\|I\|IM | |
| 3 | 0x3 | [(P)] DIV [.sat] <exec_size><dst> <src0> <src1> | Exec_size (ub): NO LIMIT | - Types: FLOAT|INT |
| | | | Dst (V_OPND): G\|I | - ".sat" only works in float type |
| | | | Src0 (V_OPND): G\|I\|IM | |
| | | | Src1 (V_OPND): G\|I\|IM | |
| 4 | 0x4 | [(P)] DP2 [.sat] <exec_size> <dst> <src0> <src1> | Exec_size (ub): >=4 | - Types: FLOAT |
| | | | Dst (V_OPND): G\|I | - The horizontal stride of dst, src0, and src1 must be 1 |
| | | | Src0 (V_OPND): G\|I\|IM | |
| | | | Src1 (V_OPND): G\|I\|IM | |
| 5 | 0x5 | [(P)] DP3 [.sat] <exec_size> <dst> <src0> <src1> | Exec_size (ub): >=4 | - Types: FLOAT |
| | | | Dst (V_OPND): G\|I | - The horizontal stride of dst, src0, and src1 must be 1 |
| | | | Src0 (V_OPND): G\|I\|IM | |
| | | | Src1 (V_OPND): G\|I\|IM | |
| 6 | 0x6 | [(P)] DP4 [.sat] <exec_size> <dst> <src0> <src1> | Exec_size (ub): >=4 | - Types: FLOAT |
| | | | Dst (V_OPND): G\|I | - The horizontal stride of dst, src0, and src1 must be 1 |
| | | | Src0 (V_OPND): G\|I\|IM | |
| | | | Src1 (V_OPND): G\|I\|IM | |
| 7 | 0x7 | [(P)] DPH [.sat] <exec_size> <dst> <src0> <src1> | Exec_size (ub): >=4 | - Types: FLOAT |
| | | | Dst (V_OPND): G\|I | - The horizontal stride of dst, src0, and src1 must be 1 |
| | | | Src0 (V_OPND): G\|I\|IM | |
| | | | Src1 (V_OPND): G\|I\|IM | |
| 8 | 0x8 | [(P)] EXP [.sat] <exec_size> <dst> <src0> | Exec_size (ub): NO LIMIT | - Types: FLOAT |
| | | | Dst (V_OPND): G\|I | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| 9 | 0x9 | [(P)] FRC <exec_size> <dst> <src0> | Exec_size (ub): NO LIMIT | - Types: FLOAT |
| | | | Dst (V_OPND): G\|I | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| 10 | 0xA | [(P)] LINE [.sat] <exec_size> <dst> <src0> <src1> | Exec_size (ub): >=4 | - Types: FLOAT|INT |
| | | | Dst (V_OPND): G\|I | - Src0's horizontal and vertical stride must be 0 |
| | | | Src0 (V_OPND): G | |
| | | | Src1 (V_OPND): G\|I\|IM | |
| 11 | 0xB | [(P)] LOG [.sat] <exec_size> <dst> <src0> | Exec_size (ub): NO LIMIT | - Types: FLOAT |
| | | | Dst (V_OPND): G\|I | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| 12 | 0xC | [(P)] MAD[.sat] <exec_size> <dst> <src0> <src1> <src2> | Exec_size (ub): NO LIMIT | - Types: FLOAT|INT |
| | | | Dst (V_OPND): G\|I | - [.sat] only works for FLOAT |
| | | | Src0 (V_OPND): G\|I:M | |
| | | | Src1 (V_OPND): G\|I\|IM | |
| | | | Src12(V_OPND): G\|I\|IM | |
| 13 | 0xD | [(P)] MULH <exec_size> <dst> <src0> <src1> | Exec_size (ub): NO LIMIT | - Types: INT|UD|D |
| | | | Dst (V_OPND): G\|I | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| | | | Src1 (V_OPND): G\|I\|IM | |
| 14 | 0xE | Reserved | | |
| 15 | 0xF | [(P)] MOD <exec_size> <dst> <src0> <src1> | Exec_size (ub): NO LIMIT | - Types: INT |
| | | | Dst (V_OPND): G\|I | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| | | | Src1 (V_OPND): G\|I\|IM | |
| 16 | 0x10 | [(P)] MUL [.sat] <exec_size> <dst> <src0> <src1> | Exec_size (ub): NO LIMIT | - Types: FLOAT|INT |
| | | | Dst (V_OPND): G\|I | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| | | | Src1 (V_OPND): G\|I\|IM | |
| 17 | 0x11 | [(P)] POW [.sat] <exec_size> <dst> <src0> <src1> | Exec_size (ub): NO LIMIT | - Types: FLOAT |
| | | | Dst (V_OPND): G\|I | - Src1's horizontal and vertical stride must be 0 |
| | | | Src0 (V_OPND): G\|I\|IM | |
| | | | Src1 (V_OPND): G\|I | |
| 18 | 0x12 | [(P)] RNDD [.sat] <exec_size> <dst> <src0> | Exec_size (ub): NO LIMIT | - Types: FLOAT |
| | | | Dst (V_OPND): G\|I | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| 19 | 0x13 | [(P)] RNDU [.sat] <exec_size> <dst> <src0> | Exec_size (ub): NO LIMIT | - Types: FLOAT |
| | | | Dst (V_OPND): G\|I | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| 20 | 0x14 | [(P)] RNDE [.sat] <exec_size> <dst> <src0> | Exec_size (ub): NO LIMIT | - Types: FLOAT |
| | | | Dst (V_OPND): G\|I | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| 21 | 0x15 | [(P)] RNDZ [.sat] <exec_size> <dst> <src0> | Exec_size (ub): NO LIMIT | - Types: FLOAT |
| | | | Dst (V_OPND): G\|I | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| 22 | 0x16 | [(P)] SAD2 [.sat] <exec_size> <dst> <src0> <src1> | Exec_size (ub): NO LIMIT | - Dst Type: W|UW |
| | | | Dst (V_OPND): G\|I | - Dst horizontal stride: 2 |
| | | | Src0 (V_OPND): G\|I\|IM | - Src0 Type: B:UB |
| | | | Src1 (V_OPND): G\|I | - Src1 Type: B:UB |
| 23 | 0x17 | [(P)] SIN [.sat] <exec_size> <dst> <src0> | Exec_size (ub): NO LIMIT | - Types: FLOAT |
| | | | Dst (V_OPND): G\|I | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| 24 | 0x18 | [(P)] COS [.sat] <exec_size> <dst> <src0> | Exec_size (ub): NO LIMIT | - Types: FLOAT |
| | | | Dst (V_OPND): G\|I | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| 25 | 0x19 | [(P)] SQRT [.sat] <exec_size> <dst> <src0> | Exec_size (ub): NO LIMIT | - Types: FLOAT |
| | | | Dst (V_OPND): G\|I | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| 26 | 0x1A | [(P)] RSQRT [.sat] <exec_size> <dst> <src0> | Exec_size (ub): NO LIMIT | - Types: FLOAT |
| | | | Dst (V_OPND): G\|I | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| 27 | 0x1B | [(P)] INV [.sat] <exec_size> <dst> <src0> | | Exec_size (ub): NO LIMIT | - Types: FLOAT |
| | | | | Dst (V_OPND): G\|I | |
| | | | | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| 28 | 0x1C | [(P)] ASIN [.sat] <exec_size> <dst> <src0> | Exec_size (ub): NO LIMIT | - Types: FLOAT |
| | | | Dst (V_OPND): G\|I | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| 29 | 0x1d | [(P)] ACOS [.sat] <exec_size> <dst> <src0> | Exec_size (ub): No limit | - Types: FLOAT |
| | | | Dst (V_OPND): G\|I | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| 30 | 0x1E | [(P)] ATAN [.sat] <exec_size> <dst> <src0> | Exec_size (ub): NO LIMIT | - Types: FLOAT |
| | | | Dst (V_OPND): G\|I | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| 31 | 0x1F | [(P)] LZD <exec_size> <dst> <src0> | Exec_size (ub): NO LIMIT | - Types: UD |
| | | | Dst (V_OPND): G\|I | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| | | | | |
| | | | | |
| 32 | 0x20 | [(P)] AND <exec_size> <dst> <src0> <src1> | Exec_size (ub): NO LIMIT | - "[(P)]" only exists for non-predication operands. |
| | | | Dst (V_OPND): G\|I\|P | - Types: INT|P |
| | | | Src0 (V_OPND): G\|I\| P\|IM | - Single data type for all operands |
| | | | Src1 (V_OPND): G\|I\|P\|IM | |
| 33 | 0x21 | [(P)] OR <exec_size> <dst> <src0> <src1> | Exec_size (ub): NO LIMIT | - "[(P)]" only exists for non-predication operands. |
| | | | Dst (V_OPND): G\|I\|P | - Types: INT|P |
| | | | Src0 (V_OPND): G\|I\| P\|IM | - Single data type for all operands |
| | | | Src1 (V_OPND): G\|I\|P\|IM | |
| 34 | 0x22 | [(P)] XOR <exec_size> <dst> <src0> <src1> | Exec_size (ub): NO LIMIT | - "[(P)]" only exists for non-predication operands. |
| | | | Dst (V_OPND): G\|I\|P | - Types: INT|P |
| | | | Src0 (V_OPND): G\|I\| P\|IM | - Single data type for all operands |
| | | | Src1 (V_OPND): G\|I\|P\|IM | |
| 35 | 0x23 | [(P)] NOT <exec_size> <dst> <src0> | Exec_size (ub): NO LIMIT | - "[(P)]" only exists for non-predication operands. |
| | | | Dst (V_OPND): G\|I\|P | - Types: INT|P |
| | | | Src0 (V_OPND): G\|I\| P\|IM | - Single data type for all operands |
| | | | Src1 (V_OPND): G\|I\|P\|IM | |
| 36 | 0x24 | [(P)] SHL <exec_size> <dst> <src0> <src1> | Exec_size (ub): NO LIMIT | - Type: INT |
| | | | Dst (V_OPND): G\|I | - Dst and Src0 may have different types |
| | | | Src0 (V_OPND):G\|I\|IM | - Src1: only 5 LSB bits work |
| | | | Src1 (V_OPND): G\|I\|IM | |
| 37 | 0x25 | [(P)] SHR <exec_size> <dst> <src0> <src1> | Exec_size (ub): NO LIMIT | - Type: INT |
| | | | Dst (V_OPND): G\|I | - Dst and Src0 may have different types |
| | | | Src0 (V_OPND):G\|I\|IM | - Src1: only 5 LSB bits work |
| | | | Src1 (V_OPND): G\|I\|IM | |
| 38 | 0x26 | [(P)] ASR <exec_size> <dst> <src0> <src1> | Exec_size (ub): NO LIMIT | - Type: INT |
| | | | Dst (V_OPND): G\|I | - Dst and Src0 may have different types |
| | | | Src0 (V_OPND):G\|I\|IM | - Src1: only 5 LSB bits work |
| | | | Src1 (V_OPND): G\|I\|IM | |
| 39 | 0x27 | reserved | | |
| 40 | 0x28 | ADDR_ADD <exec_size> <dst> <src0> <src1> | Exec_size (ub): <=8 | - Dst: right aligned |
| | | | Dst (V_OPND): A | - Src0(AO): |
| | | | Src0 (V_OPND):A\|AO | - Implicit region <0;1,0> |
| | | | Src1 (V_OPND):G\|IM | - Dst point to same gen variable |
| | | | | - Src1: UW |
| 41 | 0x29 | [(P)] MOV <exec_size> <dst> <src0> | Exec_size (ub): NO LIMIT | - Type conversion when Dst and Src0 have different data types |
| | | | Dst (V_OPND): G\|I\|A | - Src0(AO)->Dst(A) |
| | | | Src0 (V_OPND): G\|I\|IM\|P \|AO | |
| 42 | 0x2A | [(P)] SEL <exec_size> <dst> <src0> <src1> | Exec_size (ub): NO LIMIT | - Consistent type required for Dst, Src0 and Src1. |
| | | | Dst (V_OPND): G\|I | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| | | | Src1 (V_OPND): G\|I\|IM | |
| 43 | 0x2B | SETP <exec_size> <dst> <src0> | Exec_size (ub): NO LIMIT | - Src0 Type: INT |
| | | | Dst (V_OPND): P | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| 44 | 0x2C | CMP.<rel_op> <exec_size> <dst> <src0> <src1> | Exec_size (ub): NO LIMIT | |
| | | | Rel_op(ub): EQ\| NE\| GT\| | |
| | | | GE\| LT\| LE | |
| | | | Dst (V_OPND): P | |
| | | | Src0 (V_OPND): G\|I\|IM | |
| | | | Src1 (V_OPND): G\|I\|IM | |
| 45 | 0x2D | MOVS (1) <dst> <src0> | | Exec_size (ub): 1 | - Dst and Src0 have same type which is one of Sampler or Surface |
| | | | | Dst: S\|T | |
| | | | | |
| | | | Src0: S\|T | |
| 46 | 0x2E~0x2F | reserved | | |
| 48 | 0x30 | FUNC <label> | Label(uw) : Index of the label variable | - Exists only in vISA binary code |
| 49 | 0x31 | LABEL <label> | Label(uw) : Index of the label variable | - Exists only in vISA binary code |
| 50 | 0x32 | [(P)] JMP <exec_size> <label> | Exec_size (ub): 1. | |
| | | | Label:BL | |
| 51 | 0x33 | [(P)] CALL <exec_size> <label> | Exec_size (ub): 1. | |
| | | | Label (uw): FL | |
| 52 | 0x34 | [(P)] RET (exec_size) | Exec_size (ub): 1. | |
| 53 | 0x35 | OWORD_LD[.mod] (<size>) <surface> <offset> <dst> | Size (ub): 1\|2\|4\|8 | - Offset (G|IM): Scalar region |
| | | | Surface: T | - Offset(IM): UD |
| | | | Offset (V_OPND): G\|I\|IM | - Dst (R_OPND): |
| | | | Dst (R_OPND): G | - Dst: GRF-ALIGNED |
| | | | | - Dst: sizeof(Dst) >= Size |
| 54 | 0x36 | OWORD_ST (<size>) <surface> <offset> <src> | Size (ub): 1\|2\|4\|8 | - Offset (G|IM): Scalar region |
| | | | Surface: T | - Offset(IM): UD |
| | | | Offset (V_OPND): G\|I\|IM | - Dst (R_OPND): |
| | | | Dst (R_OPND): G | - Dst: GRF-ALIGNED |
| | | | | - Dst: sizeof(Dst) >= Size |
| 55 | 0x37 | MEDIA_LD.<mods> (<block_width>, <block_height>) <surface> "[" <plane> "]" <x_offset> <y_offset> <dst> | | Mods(ub): nomod\|modified\|top\|bottom\|top_mod\|bottom_mod | - Plane (ub): [0, 3] |
| | | | | Surface (ub): T | - Block_width (ub): [1, 32] |
| | | | | - Block_height (ub): [1, 64] |
| | | | | Plane (ub): IM | - X_offset (G|I): Scalar region |
| | | | | Block_width (ub): IM | - X_offset(IM): UD |
| | | | | Block_height (ub): IM | - Y_offset (G|I): Scalar region |
| | | | | X_offset (V_OPND): G\|I\|IM | - Y_offset (IM): UD |
| | | | | Y_offset (V_OPND): G\|I\|IM | - Dst (R_OPND): |
| | | | | Dst (R_OPND): G | - Dst: GRF-aligned |
| | | | | - Dst: Sizeof(Dst) >= block_height - block_width ? |
| | | | | - Dst: sizeof(Dst) >= Size |
| 56 | 0x38 | MEDIA_ST.<mods> (<block_width>, <block_height>) <surface>"["<plane>"]" <x_offset> <y_offset> <src> | | Mods(ub): nomod\|reserved\|top \|bottom | - Plane (ub): [0, 3] |
| | | | | Surface (ub): T | - Block_width (ub): [1, 32] |
| | | | | - Block_height (ub): [1, 64] |
| | | | | Plane (ub): IM | - X_offset (G|I): Scalar region |
| | | | | Block_width (ub): IM | - X_offset(IM): UD |
| | | | | Block_height (ub): IM | - Y_offset (G|I): Scalar region |
| | | | | X_offset (V_OPND): G\|I\|IM | - Y_offset (IM): UD |
| | | | | Y_offset (V_OPND): G\|I\|IM | - Dst (R_OPND): |
| | | | | Src (R_OPND): G | - Dst: GRF-aligned |
| | | | | - Dst: Sizeof(Dst) >= block_height - block_width ? |
| | | | | - Dst: sizeof(Dst) >= Size |
| 57 | 0x39 | GATHER[.mod] (<num_elts>) (<elt_size>) <surface> <global offset> <element offset> <dst> | Num_elts (ub): 8\|16 | - Global Offset:UD |
| | | | Elt_size (ub): 1\|2\|4 | - Element Offset: UD |
| | | | Surface (ub): T | - Element Offset: GRF-aligned |
| | | | Global Offset (V_OPND): G\|I\|IM | - Dst Type: UD|D|F |
| | | | Element Offset (R_OPND): G | - Dst: GRF-aligned |
| | | | Dst (R_OPND): G | - 1 and 2 byte accesses, the upper bits of Dst element will be ignored |
| | | | | |
| | | | | |
| | | | | |
| 58 | 0x3A | SCATTER (<num_elts>) (<elt_size>) <surface> <global offset> <element offset> <src> | Num_elts (ub): 8\|16 | - Global Offset:UD |
| | | | Elt_size (ub): 1\|2\|4 | - Element Offset: UD |
| | | | Surface (ub): T | - Element Offset: GRF-aligned |
| | | | Global Offset (V_OPND): G\|I\|IM | - Dst Type: UD|D|F |
| | | | Element Offset (R_OPND): G | - Dst: GRF-aligned |
| | | | Src (R_OPND): G | - 1 and 2 byte accesses, the upper bits of Dst element will be ignored |
| | | | | |
| | | | | |
| 59 | 0x3B | DWORD_ATOMIC[.<atomic_op>] (<num_elts>) <surface> <global offset> <element offset> <dst> <src0> <src1> | atomic_op(ub):ADD\|SUB\|INC \|DEC\|MIN\|MAX\| XCHG\| CMPXCHG \|AND \|OR \|XOR \|IMIN\|IMAX | - Global Offset Type:UD |
| | | | Num_elts (ub):8\|16 | Src0 (INC|DEC): V0 |
| | | | Surface (ub): T | - Src0 Type(IMIN|IMAX): D |
| | | | Global Offset (V_OPND): G\|I\|IM | - Src0 Type(others): UD |
| | | | Element Offset (R_OPND): G | - Src0: GRF-aligned |
| | | | Src0 (R_OPND): G | - Src1 Type: UD |
| | | | Src1 (R_OPND): G | - Src1: GRF-aligned |
| | | | Dst (R_OPND):G | - Src1: work only for CMPXCHG |
| | | | | - Dst: GRF-aligned |
| | | | | - Dst(IMIN|IMAX) Type:D |
| | | | | - Dst (others) Type:UD |
| 60 | 0x3C | OWORD_LD_UNALIGNED[.mod] (<size>) <surface> <offset> <dst> | Size (ub): 1\|2\|4\|8 | - Offset (G|I): Scalar region |
| | | | Surface (ub): T | - Offset Type: UD |
| | | | Offset (V_OPND): G\|I\|IM | - Dst: GRF-ALIGNED |
| | | | Dst (R_OPND): G | - Dst: sizeof(Dst) >= Size*sizeof(Oword) |
| | | | | |
| 61 | 0x3D~0x3F | Reserved | | |
| 64 | 0x40 | SAMPLE.<channel> (<SIMD_mode>) <surface> <sampler> <u_offset> <v_offset> <r_offset> <dst> | channel: [R, G, B, A, RG, RB, RA, RGB, ... RGBA] | - U_offset Type:F, GRF-aligned |
| | | | SIMD_mode: SIMD8\| SIMD16 | - V_offset Type:F, GRF-aligned |
| | | | Sampler (ub): S | - R_offset Type:F, GRF-aligned |
| | | | Surface (ub): T | - U_offset Type:F, GRF-aligned |
| | | | U_offset (R_OPND):G | - Dst Type:F, GRF-aligned |
| | | | V_offset (R_OPND):G | - Dst (SIMD8): elem_num(Dst)>=32 |
| | | | R_offset (R_OPND):G | - Dst (SIMD16): elem_num(Dst) >=16 * enabled_channels |
| | | | Dst (R_OPND):G | |
| 65 | 0x41 | SAMPLE_UNORM.<channel> <surface> <sampler> <u_offset> <v_offset> <deltaU> <deltaV> <dst> | channel: [R, G, B, A, RG, RB, RA, RGB, ... RGBA] | - U_offse Type: F |
| | | | | - V_offset Type: F |
| | | | Sampler (ub): S | deltaU Type: F |
| | | | | deltaV Type: F |
| | | | Surface (ub): T | Dst Type:UW |
| | | | | - Dst elemnum>enabled_channels*32 |
| | | | | U_offset (R_OPND): G\|I\|IM | - Dst : GRF-aligned |
| | | | | V_offset (R_OPND): G\|I\|IM | |
| | | | | deltaU (V_OPND):G\|I\|IM | |
| | | | | deltaV: (V_OPND):G\|I\|IM | |
| | | | | Dst (R_OPND):G | |
| 66 | 0x42 | LOAD.<channel> (<SIMD_mode>) <surface> <u_offset> <v_offset> <r_offset> <dst> | channel: [R, G, B, A, RG, RB, RA, RGB, ... RGBA] | - U_offset Type:F |
| | | | | - V_offset Type: F |
| | | | | SIMD_mode: SIMD8\| SIMD16 | - R_offset Type:F |
| | | | | Sampler (ub): S | - Dst Type:UW |
| | | | | Surface (ub): T | - Dst elem_num > channels*32 |
| | | | | U_offset (R_OPND):G | - Dst: GRF-aligned |
| | | | | V_offset (R_OPND):G | |
| | | | | R_offset (R_OPND):G | |
| | | | | Dst (R_OPND):G | |
| 67 | 0x43 | AVS | | |
| 68 | 0x44 | VA | | |
| 69 | 0x45 | FMINMAX | | |
| 70 | 0x46 | BFE | | |
| 71 | 0x47 | BFI | | |
| 72 | 0x48 | BFREV | | |
| 73 | 0x49 | ADDC | | |
| 74 | 0x4A | SUBB | | |
| 75 | 0x4B | GATHER4_TYPED | | |
| 76 | 0x4C | SCATTER4_TYPED | | |
| 77 | 0x4D | VA+ | | |
| 78 | 0x4E | SVM | | |
| 79-80 | 0x4F-50 | Reserved | | |
| 81 | 0x51 | FILE <file_name> | File_name(uw):FILE_NAME | - Exists only in vISA binary code |
| | | | | - File_name >= 0 |
| | | | | - Stlen(StringPool[File_name])<256 |
| | | | | |
| 82 | 0x52 | LOC <line_number> | Line_number(ud): IM | - Exists only in vISA binary code |
| | | | | - line_number >= 0 |
| 83 | 0x53 | Reserved | | |
| 84 | 0x54 | VME_SIC <surface> <UNIInput> <SICInput> <output> | Surface (ub): T | - UNIInput Types:UB |
| | | | | - UNIInput elem_num : 96 |
| | | | UNIInput(R_OPND):G | - SICInput Types:UB |
| | | | | - SICInput elem_num: 128 |
| | | | SICInput (R_OPND):G | - output Types:UB |
| | | | | - output(dis) size: 224 |
| | | | output(R_OPND):G | |
| 85 | 0x55 | VME_FBR (<FBRMbMode> <FBRSubMbShape> <FBRSubPredMode>) <surface> <UNIInput> <FBRInput> <output> | FBRMbMode(ub):16x16\|16x8\|8x16\|8x8 | - UNIInput Types:UB |
| | | | | - UNIInput elem_num : 96 |
| | | | FBRSubMbShape(ub):IM | - FBRInput Types:UB |
| | | | | - FBRInput elem_num: 128 |
| | | | FBRSubPredMode(ub):IM | - output Types:UB |
| | | | | - output(dis) size: 224 |
| | | | Surface (ub): T | |
| | | | | |
| | | | UNIInput(R_OPND):G | |
| | | | | |
| | | | FBRInput (R_OPND):G | |
| | | | | |
| | | | output(R_OPND):G | |
| 89 | 0x59~0x5f | reserved | | |
| 96 | 0x60 | [(P)] IF <exec_size> | Exec_size (ub): NO LIMIT | - start_offset value: 0|4|8|12|16|20|24|28|32|NoneSIMD |
| | | | | - start_offset value + exec_size < current_SIMD_block_width |
| | | | Start_offset: M1\|M2\|M3 \|M4\|M5\|M6\|M7\|M8\|NM | |
| | | | | |
| 97 | 0x61 | ELSE <exec_size> | Exec_size (ub): NO LIMIT | - start_offset value: 0|4|8|12|16|20|24|28|32|NoneSIMD |
| | | | | - start_offset value + exec_size < current_SIMD_block_width |
| | | | Start_offset: M1\|M2\|M3 \|M4\|M5\|M6\|M7\|M8\|NM | |
| | | | | |
| 98 | 0x62 | ENDIF <exec_size> | Exec_size (ub): NO LIMIT | - start_offset value: 0|4|8|12|16|20|24|28|32|NoneSIMD |
| | | | | - start_offset value + exec_size < current_SIMD_block_width |
| | | | Start_offset: M1\|M2\|M3 \|M4\|M5\|M6\|M7\|M8\|NM | |
| | | | | |
| 99 | 0x63 | DO <exec_size> | Exec_size (ub): NO LIMIT | - start_offset value: 0|4|8|12|16|20|24|28|32|NoneSIMD |
| | | | | - start_offset value + exec_size < current_SIMD_block_width |
| | | | Start_offset: M1\|M2\|M3 \|M4\|M5\|M6\|M7\|M8\|NM | |
| | | | | |
| 100 | 0x64 | [(P)] WHILE <exec_size> | Exec_size (ub): NO LIMIT | - start_offset value: 0|4|8|12|16|20|24|28|32|NoneSIMD |
| | | | | - start_offset value + exec_size < current_SIMD_block_width |
| | | | Start_offset: M1\|M2\|M3 \|M4\|M5\|M6\|M7\|M8\|NM | |
| | | | | |
| 101 | 0x65 | [(P)] BREAK <exec_size> | Exec_size (ub): NO LIMIT | - start_offset value: 0|4|8|12|16|20|24|28|32|NoneSIMD |
| | | | | - start_offset value + exec_size < current_SIMD_block_width |
| | | | Start_offset: M1\|M2\|M3 \|M4\|M5\|M6\|M7\|M8\|NM | |
| | | | | |
| 102 | 0x66 | [(P)] CONT <exec_size> | Exec_size (ub): NO LIMIT | - start_offset value: 0|4|8|12|16|20|24|28|32|NoneSIMD |
| | | | | - start_offset value + exec_size < current_SIMD_block_width |
| | | | Start_offset: M1\|M2\|M3 \|M4\|M5\|M6\|M7\|M8\|NM | |
| | | | | |
Notation:
Execution size must be then number which is powers-of-two from 1 to 32,
not matter "NO LIMIT" or range specified.
If the predicate is "P0", this means the instruction is not predicated.
Except the MOV instruction, and predicate operand, all the instructions
should have consistent data type for other vector operands.
.. UNREFERENCED_FOOTNOTE [1]
vISA 3.1 and earlier has the offsets in dwords
|
