1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
|
;=========================== begin_copyright_notice ============================
;
; Copyright (C) 2022 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
;============================ end_copyright_notice =============================
;
; RUN: igc_opt --platformdg2 --igc-PartialEmuI64Ops -S < %s 2>&1 | FileCheck %s
; ------------------------------------------------
; PartialEmuI64Ops : Unaffected instructions check
; ------------------------------------------------
; Test checks unaffected by pass i64 ops
define void @test_double(double %src1, double %src2) {
; CHECK-LABEL: @test_double(
; CHECK-NEXT: [[TMP1:%.*]] = fadd double [[SRC1:%.*]], [[SRC2:%.*]]
; CHECK-NEXT: call void @use.f64(double [[TMP1]])
; CHECK-NEXT: [[TMP2:%.*]] = fsub double [[SRC1]], [[SRC2]]
; CHECK-NEXT: call void @use.f64(double [[TMP2]])
; CHECK-NEXT: [[TMP3:%.*]] = fdiv double [[SRC1]], [[SRC2]]
; CHECK-NEXT: call void @use.f64(double [[TMP3]])
; CHECK-NEXT: [[TMP4:%.*]] = frem double [[SRC1]], [[SRC2]]
; CHECK-NEXT: call void @use.f64(double [[TMP4]])
; CHECK-NEXT: [[TMP5:%.*]] = fmul double [[SRC1]], [[SRC2]]
; CHECK-NEXT: call void @use.f64(double [[TMP5]])
; CHECK-NEXT: [[TMP6:%.*]] = fcmp one double [[SRC1]], [[SRC2]]
; CHECK-NEXT: call void @use.i1(i1 [[TMP6]])
; CHECK-NEXT: [[TMP7:%.*]] = fptrunc double [[SRC1]] to float
; CHECK-NEXT: call void @use.f32(float [[TMP7]])
; CHECK-NEXT: [[TMP8:%.*]] = fpext float [[TMP7]] to double
; CHECK-NEXT: call void @use.f64(double [[TMP8]])
; CHECK-NEXT: [[TMP9:%.*]] = fptosi double [[SRC1]] to i64
; CHECK-NEXT: call void @use.i64(i64 [[TMP9]])
; CHECK-NEXT: [[TMP10:%.*]] = fptoui double [[SRC1]] to i64
; CHECK-NEXT: call void @use.i64(i64 [[TMP10]])
; CHECK-NEXT: [[TMP11:%.*]] = sitofp i64 [[TMP9]] to double
; CHECK-NEXT: call void @use.f64(double [[TMP11]])
; CHECK-NEXT: ret void
;
%1 = fadd double %src1, %src2
call void @use.f64(double %1)
%2 = fsub double %src1, %src2
call void @use.f64(double %2)
%3 = fdiv double %src1, %src2
call void @use.f64(double %3)
%4 = frem double %src1, %src2
call void @use.f64(double %4)
%5 = fmul double %src1, %src2
call void @use.f64(double %5)
%6 = fcmp one double %src1, %src2
call void @use.i1(i1 %6)
%7 = fptrunc double %src1 to float
call void @use.f32(float %7)
%8 = fpext float %7 to double
call void @use.f64(double %8)
%9 = fptosi double %src1 to i64
call void @use.i64(i64 %9)
%10 = fptoui double %src1 to i64
call void @use.i64(i64 %10)
%11 = sitofp i64 %9 to double
call void @use.f64(double %11)
ret void
}
define void @test_shift_trunc(i64 %src1) {
; CHECK-LABEL: @test_shift_trunc(
; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[SRC1:%.*]], 3
; CHECK-NEXT: call void @use.i64(i64 [[TMP1]])
; CHECK-NEXT: [[TMP2:%.*]] = ashr i64 [[SRC1]], 2
; CHECK-NEXT: call void @use.i64(i64 [[TMP2]])
; CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[SRC1]], 2
; CHECK-NEXT: call void @use.i64(i64 [[TMP3]])
; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[SRC1]] to i32
; CHECK-NEXT: call void @use.i32(i32 [[TMP4]])
; CHECK-NEXT: [[TMP5:%.*]] = sext i32 [[TMP4]] to i64
; CHECK-NEXT: call void @use.i64(i64 [[TMP5]])
; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[TMP4]] to i64
; CHECK-NEXT: call void @use.i64(i64 [[TMP6]])
; CHECK-NEXT: ret void
;
%1 = lshr i64 %src1, 3
call void @use.i64(i64 %1)
%2 = ashr i64 %src1, 2
call void @use.i64(i64 %2)
%3 = shl i64 %src1, 2
call void @use.i64(i64 %3)
%4 = trunc i64 %src1 to i32
call void @use.i32(i32 %4)
%5 = sext i32 %4 to i64
call void @use.i64(i64 %5)
%6 = zext i32 %4 to i64
call void @use.i64(i64 %6)
ret void
}
define void @test_vector(<2 x i64> %src1) {
; CHECK-LABEL: @test_vector(
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i64> [[SRC1:%.*]], i32 1
; CHECK-NEXT: call void @use.i64(i64 [[TMP1]])
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> [[SRC1]], i64 [[TMP1]], i32 0
; CHECK-NEXT: call void @use.2i64(<2 x i64> [[TMP2]])
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i64> [[SRC1]], <2 x i64> [[TMP2]], <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: call void @use.2i64(<2 x i64> [[TMP3]])
; CHECK-NEXT: ret void
;
%1 = extractelement <2 x i64> %src1, i32 1
call void @use.i64(i64 %1)
%2 = insertelement <2 x i64 > %src1, i64 %1, i32 0
call void @use.2i64(<2 x i64> %2)
%3 = shufflevector <2 x i64> %src1, <2 x i64> %2, <2 x i32> <i32 0, i32 1>
call void @use.2i64(<2 x i64> %3)
ret void
}
define void @test_switch(i64 %src1) {
; CHECK-LABEL: @test_switch(
; CHECK-NEXT: entry:
; CHECK-NEXT: switch i64 [[SRC1:%.*]], label [[BR3:%.*]] [
; CHECK-NEXT: i64 -5, label [[BR1:%.*]]
; CHECK-NEXT: i64 -4, label [[BR2:%.*]]
; CHECK-NEXT: ]
; CHECK: br1:
; CHECK-NEXT: br label [[END:%.*]]
; CHECK: br2:
; CHECK-NEXT: br label [[END]]
; CHECK: br3:
; CHECK-NEXT: br label [[END]]
; CHECK: end:
; CHECK-NEXT: [[TMP0:%.*]] = phi i64 [ 15, [[BR3]] ], [ 16, [[BR1]] ], [ 17, [[BR2]] ]
; CHECK-NEXT: call void @use.i64(i64 [[TMP0]])
; CHECK-NEXT: ret void
;
entry:
switch i64 %src1, label %br3 [
i64 -5, label %br1
i64 -4, label %br2
]
br1:
br label %end
br2:
br label %end
br3:
br label %end
end: ; preds = %br3, %br2, %br1
%0 = phi i64 [ 15, %br3 ], [ 16, %br1 ], [ 17, %br2 ]
call void @use.i64(i64 %0)
ret void
}
declare void @use.f64(double)
declare void @use.f32(float)
declare void @use.2i64(<2 x i64>)
declare void @use.i64(i64)
declare void @use.i32(i32)
declare void @use.i1(i1)
!igc.functions = !{!0, !3, !4, !5}
!0 = !{void (double, double)* @test_double, !1}
!1 = !{!2}
!2 = !{!"function_type", i32 0}
!3 = !{void (i64)* @test_shift_trunc, !1}
!4 = !{void (<2 x i64>)* @test_vector, !1}
!5 = !{void (i64)* @test_switch, !1}
|
