1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
|
;=========================== begin_copyright_notice ============================
;
; Copyright (C) 2024 Intel Corporation
;
; SPDX-License-Identifier: MIT
;
;============================ end_copyright_notice =============================
; REQUIRES: llvm-14-plus
; RUN: igc_opt --opaque-pointers -TrivialLocalMemoryOpsElimination -S < %s | FileCheck %s
; ------------------------------------------------
; TrivialLocalMemoryOpsElimination
; ------------------------------------------------
; This test checks that dead local load/stores and barriers
; are removed by this pass
; ------------------------------------------------
define spir_kernel void @test_load(i32 addrspace(3)* %b) {
; CHECK-LABEL: @test_load(
; CHECK-NEXT: ret void
%1 = load i32, i32 addrspace(3)* %b, align 4
ret void
}
define spir_kernel void @test_store(i32 addrspace(3)* %b) {
; CHECK-LABEL: @test_store(
; CHECK-NEXT: ret void
store i32 13, i32 addrspace(3)* %b, align 4
ret void
}
define spir_kernel void @test_barrier_remove(i32 addrspace(3)* %b) {
; CHECK-LABEL: @test_barrier_remove(
; CHECK-NEXT: ret void
store i32 14, i32 addrspace(3)* %b, align 4
call void @llvm.genx.GenISA.memoryfence(i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true)
call void @llvm.genx.GenISA.threadgroupbarrier()
ret void
}
define spir_kernel void @test_barrier_keep(i32 addrspace(3)* %b) {
; CHECK-LABEL: @test_barrier_keep(
; CHECK-NEXT: call void @llvm.genx.GenISA.memoryfence(i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true)
; CHECK-NEXT: call void @llvm.genx.GenISA.threadgroupbarrier()
; CHECK-NEXT: ret void
store i32 15, i32 addrspace(3)* %b, align 4
call void @llvm.genx.GenISA.memoryfence(i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 true)
call void @llvm.genx.GenISA.threadgroupbarrier()
ret void
}
declare void @llvm.genx.GenISA.memoryfence(i1, i1, i1, i1, i1, i1, i1)
declare void @llvm.genx.GenISA.threadgroupbarrier()
!igc.functions = !{!0, !3, !4, !5}
!0 = !{void (i32 addrspace(3)*)* @test_load, !1}
!1 = !{!2}
!2 = !{!"function_type", i32 0}
!3 = !{void (i32 addrspace(3)*)* @test_store, !1}
!4 = !{void (i32 addrspace(3)*)* @test_barrier_remove, !1}
!5 = !{void (i32 addrspace(3)*)* @test_barrier_keep, !1}
|
