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iverilog 12.0-2
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid, trixie
  • size: 30,100 kB
  • sloc: cpp: 109,972; ansic: 62,713; yacc: 10,216; sh: 3,470; vhdl: 3,246; perl: 1,814; makefile: 1,774; python: 78; csh: 2
file content (26 lines) | stat: -rw-r--r-- 1,036 bytes parent folder | download
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Source: iverilog
Section: electronics
Priority: optional
Maintainer: Debian Electronics Team <pkg-electronics-devel@alioth-lists.debian.net>
Uploaders: أحمد المحمودي (Ahmed El-Mahmoudy) <aelmahmoudy@users.sourceforge.net>
Build-Depends: debhelper-compat (= 13), gperf, bison, flex, zlib1g-dev, libbz2-dev, libreadline-dev
Rules-Requires-Root: no
Standards-Version: 4.6.2
Homepage: http://iverilog.icarus.com
Vcs-Git: https://salsa.debian.org/electronics-team/iverilog.git
Vcs-Browser: https://salsa.debian.org/electronics-team/iverilog

Package: iverilog
Architecture: any
Depends: ${shlibs:Depends}, ${misc:Depends}
Replaces: verilog (<< 10.2-1.1~)
Breaks: verilog (<< 10.2-1.1~)
Provides: verilog
Suggests: gtkwave
Description: Icarus verilog compiler
 Icarus Verilog is intended to compile all of the Verilog HDL as
 described in the IEEE-1364 standard. It is not quite there
 yet. It does currently handle a mix of structural and behavioral
 constructs.
 .
 The compiler can target either simulation, or netlist (EDIF).