File: blif01a.v

package info (click to toggle)
iverilog 12.0-3
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid
  • size: 30,148 kB
  • sloc: cpp: 109,972; ansic: 62,713; yacc: 10,216; sh: 3,470; vhdl: 3,246; perl: 1,814; makefile: 1,774; python: 78; csh: 2
file content (66 lines) | stat: -rw-r--r-- 1,491 bytes parent folder | download | duplicates (2)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66

/*
 * Generate a combinational adder of any width. The width parameter can
 * be any integer value >0. The A and B inputs have WID bits, and the Q
 * output has WID+1 bits to include the overflow.
 */
module addN
  #(parameter WID = 4)
   (input wire [WID-1:0] A,
    input wire [WID-1:0] B,
    output wire [WID:0]  Q
    /* */);

   wire [WID-1:0]	Cout;

   /* The least significant slice has no Cin */
   add1 U0 (.A(A[0]), .B(B[0]), .Cin(1'b0), .Q(Q[0]), .Cout(Cout[0]));

   /* Generate all the remaining slices */
   genvar i;
   for (i = 1 ; i < WID ; i = i+1) begin : U
      add1 Un (.A(A[i]), .B(B[i]), .Cin(Cout[i-1]), .Q(Q[i]), .Cout(Cout[i]));
   end

   assign Q[WID] = Cout[WID-1];

endmodule // add

/*
 * This is a single-bit combinational adder used by the addH module
 * above.
 */
module add1(input A, input B, input Cin, output Q, output Cout);

   assign Q = A ^ B ^ Cin;
   assign Cout = A&B | A&Cin | B&Cin;

endmodule // hadd

`ifdef TEST_BENCH
module main;

   parameter WID = 4;
   reg [WID-1:0] A, B;
   wire [WID:0]  Q;

   addN #(.WID(WID)) usum (.A(A), .B(B), .Q(Q));

   int		 adx;
   int		 bdx;
   initial begin
      for (bdx = 0 ; bdx[WID]==0 ; bdx = bdx+1) begin
	 for (adx = 0 ; adx[WID]==0 ; adx = adx+1) begin
	    A <= adx[WID-1:0];
	    B <= bdx[WID-1:0];
	    #1 if (Q !== (adx+bdx)) begin
	       $display("FAILED -- A=%b, B=%b, Q=%b", A, B, Q);
	       $finish;
	    end
	 end
      end
      $display("PASSED");
   end

endmodule // main
`endif