File: ge8.v

package info (click to toggle)
iverilog 12.0-3
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid
  • size: 30,148 kB
  • sloc: cpp: 109,972; ansic: 62,713; yacc: 10,216; sh: 3,470; vhdl: 3,246; perl: 1,814; makefile: 1,774; python: 78; csh: 2
file content (5 lines) | stat: -rw-r--r-- 105 bytes parent folder | download | duplicates (2)
1
2
3
4
5
module ge8(output wire out, input wire [7:0] A, input wire [7:0] B);

   assign out = A >= B;

endmodule