File: ornor4.v

package info (click to toggle)
iverilog 12.0-3
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid
  • size: 30,148 kB
  • sloc: cpp: 109,972; ansic: 62,713; yacc: 10,216; sh: 3,470; vhdl: 3,246; perl: 1,814; makefile: 1,774; python: 78; csh: 2
file content (7 lines) | stat: -rw-r--r-- 186 bytes parent folder | download | duplicates (2) 
1
2
3
4
5
6
7
 
module ornor4(output wire O_OR, output wire O_NOR,
	      input wire I0, I1, I2, I3);

   assign O_OR  =  | {I0, I1, I2, I3};
   assign O_NOR = ~| {I0, I1, I2, I3};

endmodule // ornor4