File: pr2516774.v

package info (click to toggle)
iverilog 12.0-3
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid
  • size: 30,148 kB
  • sloc: cpp: 109,972; ansic: 62,713; yacc: 10,216; sh: 3,470; vhdl: 3,246; perl: 1,814; makefile: 1,774; python: 78; csh: 2
file content (22 lines) | stat: -rw-r--r-- 400 bytes parent folder | download | duplicates (2)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
// Catch problem where we assign to function params
module top();
  integer r;

  function integer fact;
    input   n;
    integer n;

    for (fact = 1; n > 0; n = n - 1) begin
      fact = fact * n;
    end
  endfunction // for

  initial begin
    r = fact(5);
    $display("fact(5) = %d", r);
    if (r == 120)
      $display("PASSED");
    else
      $display("FAILED");
  end
endmodule // top