1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
|
/*
* CHRP pci routines.
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/openpic.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/irq.h>
#include <asm/hydra.h>
#include <asm/prom.h>
#include <asm/gg2.h>
/* LongTrail */
#define pci_config_addr(bus, dev, offset) \
(GG2_PCI_CONFIG_BASE | ((bus)<<16) | ((dev)<<8) | (offset))
volatile struct Hydra *Hydra = NULL;
/*
* The VLSI Golden Gate II has only 512K of PCI configuration space, so we
* limit the bus number to 3 bits
*/
int gg2_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn,
unsigned char offset, unsigned char *val)
{
if (bus > 7) {
*val = 0xff;
return PCIBIOS_DEVICE_NOT_FOUND;
}
*val = in_8((unsigned char *)pci_config_addr(bus, dev_fn, offset));
return PCIBIOS_SUCCESSFUL;
}
int gg2_pcibios_read_config_word(unsigned char bus, unsigned char dev_fn,
unsigned char offset, unsigned short *val)
{
if (bus > 7) {
*val = 0xffff;
return PCIBIOS_DEVICE_NOT_FOUND;
}
*val = in_le16((unsigned short *)pci_config_addr(bus, dev_fn, offset));
return PCIBIOS_SUCCESSFUL;
}
int gg2_pcibios_read_config_dword(unsigned char bus, unsigned char dev_fn,
unsigned char offset, unsigned int *val)
{
if (bus > 7) {
*val = 0xffffffff;
return PCIBIOS_DEVICE_NOT_FOUND;
}
*val = in_le32((unsigned int *)pci_config_addr(bus, dev_fn, offset));
return PCIBIOS_SUCCESSFUL;
}
int gg2_pcibios_write_config_byte(unsigned char bus, unsigned char dev_fn,
unsigned char offset, unsigned char val)
{
if (bus > 7)
return PCIBIOS_DEVICE_NOT_FOUND;
out_8((unsigned char *)pci_config_addr(bus, dev_fn, offset), val);
return PCIBIOS_SUCCESSFUL;
}
int gg2_pcibios_write_config_word(unsigned char bus, unsigned char dev_fn,
unsigned char offset, unsigned short val)
{
if (bus > 7)
return PCIBIOS_DEVICE_NOT_FOUND;
out_le16((unsigned short *)pci_config_addr(bus, dev_fn, offset), val);
return PCIBIOS_SUCCESSFUL;
}
int gg2_pcibios_write_config_dword(unsigned char bus, unsigned char dev_fn,
unsigned char offset, unsigned int val)
{
if (bus > 7)
return PCIBIOS_DEVICE_NOT_FOUND;
out_le32((unsigned int *)pci_config_addr(bus, dev_fn, offset), val);
return PCIBIOS_SUCCESSFUL;
}
extern volatile unsigned int *pci_config_address;
extern volatile unsigned char *pci_config_data;
#define DEV_FN_MAX (31<<3)
int raven_pcibios_read_config_byte(unsigned char bus,
unsigned char dev_fn,
unsigned char offset,
unsigned char *val)
{
if (dev_fn >= DEV_FN_MAX) return PCIBIOS_DEVICE_NOT_FOUND;
out_be32(pci_config_address,
0x80|(bus<<8)|(dev_fn<<16)|((offset&~3)<<24));
*val = in_8(pci_config_data+(offset&3));
return PCIBIOS_SUCCESSFUL;
}
int raven_pcibios_read_config_word(unsigned char bus,
unsigned char dev_fn,
unsigned char offset,
unsigned short *val)
{
if (dev_fn >= DEV_FN_MAX) return PCIBIOS_DEVICE_NOT_FOUND;
if (offset&1)return PCIBIOS_BAD_REGISTER_NUMBER;
out_be32(pci_config_address,
0x80|(bus<<8)|(dev_fn<<16)|((offset&~3)<<24));
*val = in_le16((volatile unsigned short *)
(pci_config_data+(offset&3)));
return PCIBIOS_SUCCESSFUL;
}
int raven_pcibios_read_config_dword(unsigned char bus,
unsigned char dev_fn,
unsigned char offset,
unsigned int *val)
{
if (dev_fn >= DEV_FN_MAX) return PCIBIOS_DEVICE_NOT_FOUND;
if (offset&3)return PCIBIOS_BAD_REGISTER_NUMBER;
out_be32(pci_config_address,
0x80|(bus<<8)|(dev_fn<<16)|(offset<<24));
*val = in_le32((volatile unsigned int *)(pci_config_data));
return PCIBIOS_SUCCESSFUL;
}
int raven_pcibios_write_config_byte(unsigned char bus,
unsigned char dev_fn,
unsigned char offset,
unsigned char val)
{
if (dev_fn >= DEV_FN_MAX) return PCIBIOS_DEVICE_NOT_FOUND;
out_be32(pci_config_address,
0x80|(bus<<8)|(dev_fn<<16)|((offset&~3)<<24));
out_8(pci_config_data+(offset&3),val);
return PCIBIOS_SUCCESSFUL;
}
int raven_pcibios_write_config_word(unsigned char bus,
unsigned char dev_fn,
unsigned char offset,
unsigned short val)
{
if (dev_fn >= DEV_FN_MAX) return PCIBIOS_DEVICE_NOT_FOUND;
if (offset&1)return PCIBIOS_BAD_REGISTER_NUMBER;
out_be32(pci_config_address,
0x80|(bus<<8)|(dev_fn<<16)|((offset&~3)<<24));
out_le16((volatile unsigned short *)(pci_config_data+(offset&3)),val);
return PCIBIOS_SUCCESSFUL;
}
int raven_pcibios_write_config_dword(unsigned char bus,
unsigned char dev_fn,
unsigned char offset,
unsigned int val)
{
if (dev_fn >= DEV_FN_MAX) return PCIBIOS_DEVICE_NOT_FOUND;
if (offset&3)return PCIBIOS_BAD_REGISTER_NUMBER;
out_be32(pci_config_address,
0x80|(bus<<8)|(dev_fn<<16)|(offset<<24));
out_le32((volatile unsigned int *)pci_config_data,val);
return PCIBIOS_SUCCESSFUL;
}
/*
* Temporary fixes for PCI devices. These should be replaced by OF query
* code -- Geert
*/
static u_char hydra_openpic_initsenses[] __initdata = {
1, /* HYDRA_INT_SIO */
0, /* HYDRA_INT_SCSI_DMA */
0, /* HYDRA_INT_SCCA_TX_DMA */
0, /* HYDRA_INT_SCCA_RX_DMA */
0, /* HYDRA_INT_SCCB_TX_DMA */
0, /* HYDRA_INT_SCCB_RX_DMA */
1, /* HYDRA_INT_SCSI */
1, /* HYDRA_INT_SCCA */
1, /* HYDRA_INT_SCCB */
1, /* HYDRA_INT_VIA */
1, /* HYDRA_INT_ADB */
0, /* HYDRA_INT_ADB_NMI */
/* all others are 1 (= default) */
};
__initfunc(int hydra_init(void))
{
struct device_node *np;
np = find_devices("mac-io");
if (np == NULL || np->n_addrs == 0) {
printk(KERN_WARNING "Warning: no mac-io found\n");
return 0;
}
Hydra = ioremap(np->addrs[0].address, np->addrs[0].size);
printk("Hydra Mac I/O at %x\n", np->addrs[0].address);
out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN |
HYDRA_FC_SCSI_CELL_EN |
HYDRA_FC_SCCA_ENABLE |
HYDRA_FC_SCCB_ENABLE |
HYDRA_FC_ARB_BYPASS |
HYDRA_FC_MPIC_ENABLE |
HYDRA_FC_SLOW_SCC_PCLK |
HYDRA_FC_MPIC_IS_MASTER));
OpenPIC = (volatile struct OpenPIC *)&Hydra->OpenPIC;
OpenPIC_InitSenses = hydra_openpic_initsenses;
OpenPIC_NumInitSenses = sizeof(hydra_openpic_initsenses);
return 1;
}
extern int chrp_ide_irq;
__initfunc(int w83c553f_init(void))
{
u_char bus, dev;
#if 0
unsigned char t8;
unsigned short t16;
#endif
unsigned int t32;
struct pci_dev *pdev;
if ((pdev = pci_find_device(PCI_VENDOR_ID_WINBOND,
PCI_DEVICE_ID_WINBOND_83C553, NULL))) {
bus = pdev->bus->number;
dev = pdev->devfn + 1;
pcibios_read_config_dword(bus, dev, PCI_VENDOR_ID, &t32);
if (t32 == (PCI_DEVICE_ID_WINBOND_82C105<<16) + PCI_VENDOR_ID_WINBOND) {
#if 0
printk("Enabling SL82C105 IDE on W83C553F\n");
/*
* FIXME: this doesn't help :-(
*/
/* I/O mapping */
pcibios_read_config_word(bus, dev, PCI_COMMAND, &t16);
t16 |= PCI_COMMAND_IO;
pcibios_write_config_word(bus, dev, PCI_COMMAND, t16);
/* Standard IDE registers */
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_0,
0xffffffff);
pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_0, &t32);
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_0,
0x000001f0 | 1);
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_1,
0xffffffff);
pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_1, &t32);
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_1,
0x000003f4 | 1);
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_2,
0xffffffff);
pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_2, &t32);
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_2,
0x00000170 | 1);
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_3,
0xffffffff);
pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_3, &t32);
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_3,
0x00000374 | 1);
/* IDE Bus Master Control */
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_4,
0xffffffff);
pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_4, &t32);
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_4,
0x1000 | 1);
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_5,
0xffffffff);
pcibios_read_config_dword(bus, dev, PCI_BASE_ADDRESS_5, &t32);
pcibios_write_config_dword(bus, dev, PCI_BASE_ADDRESS_5,
0x1010 | 1);
/* IDE Interrupt */
pcibios_read_config_byte(bus, dev, PCI_INTERRUPT_LINE, &t8);
chrp_ide_irq = t8;
#endif
return 1;
}
}
return 0;
}
|
