1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
|
/*
* Setup the interrupt stuff.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1998 Harald Koerfgen
* Copyright (C) 2000 Maciej W. Rozycki
*/
#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/mc146818rtc.h>
#include <linux/param.h>
#include <linux/console.h>
#include <asm/mipsregs.h>
#include <asm/bootinfo.h>
#include <linux/init.h>
#include <asm/irq.h>
#include <asm/reboot.h>
#include <asm/dec/interrupts.h>
#include <asm/dec/kn01.h>
#include <asm/dec/kn02.h>
#include <asm/dec/kn02xa.h>
#include <asm/dec/kn03.h>
#include <asm/dec/ioasic.h>
#include <asm/dec/ioasic_addrs.h>
#include <asm/dec/ioasic_ints.h>
char *dec_rtc_base = (void *) KN01_RTC_BASE; /* Assume DS2100/3100 initially */
volatile unsigned int *ioasic_base;
decint_t dec_interrupt[NR_INTS];
/*
* Information regarding the IRQ Controller
*/
volatile unsigned int *isr = 0L; /* address of the interrupt status register */
volatile unsigned int *imr = 0L; /* address of the interrupt mask register */
extern void dec_machine_restart(char *command);
extern void dec_machine_halt(void);
extern void dec_machine_power_off(void);
extern void dec_intr_halt(int irq, void *dev_id, struct pt_regs *regs);
extern void wbflush_setup(void);
extern struct rtc_ops dec_rtc_ops;
extern int setup_dec_irq(int, struct irqaction *);
void (*board_time_init) (struct irqaction * irq);
static struct irqaction irq10 = {dec_intr_halt, 0, 0, "halt", NULL, NULL};
/*
* enable the periodic interrupts
*/
static void __init dec_time_init(struct irqaction *irq)
{
/*
* Here we go, enable periodic rtc interrupts.
*/
#ifndef LOG_2_HZ
# define LOG_2_HZ 7
#endif
CMOS_WRITE(RTC_REF_CLCK_32KHZ | (16 - LOG_2_HZ), RTC_REG_A);
CMOS_WRITE(CMOS_READ(RTC_REG_B) | RTC_PIE, RTC_REG_B);
setup_dec_irq(CLOCK, irq);
}
/*
* Enable the halt interrupt.
*/
static void __init dec_halt_init(struct irqaction *irq)
{
setup_dec_irq(HALT, irq);
}
void __init decstation_setup(void)
{
board_time_init = dec_time_init;
wbflush_setup();
_machine_restart = dec_machine_restart;
_machine_halt = dec_machine_halt;
_machine_power_off = dec_machine_power_off;
#ifdef CONFIG_FB
conswitchp = &dummy_con;
#endif
rtc_ops = &dec_rtc_ops;
}
/*
* Machine-specific initialisation for kn01, aka Pmax, aka DS2100, DS3100,
* and possibly also the DS5100.
*/
void __init dec_init_kn01(void)
{
/*
* Setup some memory addresses.
*/
dec_rtc_base = (char *) KN01_RTC_BASE;
/*
* Setup interrupt structure
*/
dec_interrupt[CLOCK].cpu_mask = IE_IRQ3;
dec_interrupt[CLOCK].iemask = 0;
cpu_mask_tbl[0] = IE_IRQ3;
cpu_irq_nr[0] = CLOCK;
dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ0;
dec_interrupt[SCSI_INT].iemask = 0;
cpu_mask_tbl[1] = IE_IRQ0;
cpu_irq_nr[1] = SCSI_INT;
dec_interrupt[ETHER].cpu_mask = IE_IRQ1;
dec_interrupt[ETHER].iemask = 0;
cpu_mask_tbl[2] = IE_IRQ1;
cpu_irq_nr[2] = ETHER;
dec_interrupt[SERIAL].cpu_mask = IE_IRQ2;
dec_interrupt[SERIAL].iemask = 0;
cpu_mask_tbl[3] = IE_IRQ2;
cpu_irq_nr[3] = SERIAL;
dec_interrupt[MEMORY].cpu_mask = IE_IRQ4;
dec_interrupt[MEMORY].iemask = 0;
cpu_mask_tbl[4] = IE_IRQ4;
cpu_irq_nr[4] = MEMORY;
dec_interrupt[FPU].cpu_mask = IE_IRQ5;
dec_interrupt[FPU].iemask = 0;
cpu_mask_tbl[5] = IE_IRQ5;
cpu_irq_nr[5] = FPU;
} /* dec_init_kn01 */
/*
* Machine-specific initialisation for kn230, aka MIPSmate, aka DS5100
*
* There are a lot of experiments to do, this is definitely incomplete.
*/
void __init dec_init_kn230(void)
{
/*
* Setup some memory addresses.
*/
dec_rtc_base = (char *) KN01_RTC_BASE;
/*
* Setup interrupt structure
*/
dec_interrupt[CLOCK].cpu_mask = IE_IRQ2;
dec_interrupt[CLOCK].iemask = 0;
cpu_mask_tbl[0] = IE_IRQ2;
cpu_irq_nr[0] = CLOCK;
dec_interrupt[FPU].cpu_mask = IE_IRQ5;
dec_interrupt[FPU].iemask = 0;
cpu_mask_tbl[5] = IE_IRQ5;
cpu_irq_nr[5] = FPU;
} /* dec_init_kn230 */
/*
* Machine-specific initialisation for kn02, aka 3max, aka DS5000/2xx.
*/
void __init dec_init_kn02(void)
{
/*
* Setup some memory addresses. FIXME: probably incomplete!
*/
dec_rtc_base = (char *) KN02_RTC_BASE;
isr = (void *) KN02_CSR_ADDR;
imr = (void *) KN02_CSR_ADDR;
/*
* Setup IOASIC interrupt
*/
cpu_ivec_tbl[1] = kn02_io_int;
cpu_mask_tbl[1] = IE_IRQ0;
cpu_irq_nr[1] = -1;
*imr = *imr & 0xff00ff00;
/*
* Setup interrupt structure
*/
dec_interrupt[CLOCK].cpu_mask = IE_IRQ1;
dec_interrupt[CLOCK].iemask = 0;
cpu_mask_tbl[0] = IE_IRQ1;
cpu_irq_nr[0] = CLOCK;
dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ0;
dec_interrupt[SCSI_INT].iemask = KN02_SLOT5;
asic_mask_tbl[0] = KN02_SLOT5;
asic_irq_nr[0] = SCSI_INT;
dec_interrupt[ETHER].cpu_mask = IE_IRQ0;
dec_interrupt[ETHER].iemask = KN02_SLOT6;
asic_mask_tbl[1] = KN02_SLOT6;
asic_irq_nr[1] = ETHER;
dec_interrupt[SERIAL].cpu_mask = IE_IRQ0;
dec_interrupt[SERIAL].iemask = KN02_SLOT7;
asic_mask_tbl[2] = KN02_SLOT7;
asic_irq_nr[2] = SERIAL;
dec_interrupt[TC0].cpu_mask = IE_IRQ0;
dec_interrupt[TC0].iemask = KN02_SLOT0;
asic_mask_tbl[3] = KN02_SLOT0;
asic_irq_nr[3] = TC0;
dec_interrupt[TC1].cpu_mask = IE_IRQ0;
dec_interrupt[TC1].iemask = KN02_SLOT1;
asic_mask_tbl[4] = KN02_SLOT1;
asic_irq_nr[4] = TC1;
dec_interrupt[TC2].cpu_mask = IE_IRQ0;
dec_interrupt[TC2].iemask = KN02_SLOT2;
asic_mask_tbl[5] = KN02_SLOT2;
asic_irq_nr[5] = TC2;
dec_interrupt[MEMORY].cpu_mask = IE_IRQ3;
dec_interrupt[MEMORY].iemask = 0;
cpu_mask_tbl[2] = IE_IRQ3;
cpu_irq_nr[2] = MEMORY;
dec_interrupt[FPU].cpu_mask = IE_IRQ5;
dec_interrupt[FPU].iemask = 0;
cpu_mask_tbl[3] = IE_IRQ5;
cpu_irq_nr[3] = FPU;
} /* dec_init_kn02 */
/*
* Machine-specific initialisation for kn02ba, aka 3min, aka DS5000/1xx.
*/
void __init dec_init_kn02ba(void)
{
/*
* Setup some memory addresses.
*/
ioasic_base = (void *) KN02XA_IOASIC_BASE;
dec_rtc_base = (char *) KN02XA_RTC_BASE;
isr = (void *) KN02XA_IOASIC_REG(SIR);
imr = (void *) KN02XA_IOASIC_REG(SIMR);
/*
* Setup IOASIC interrupt
*/
cpu_mask_tbl[0] = IE_IRQ3;
cpu_irq_nr[0] = -1;
cpu_ivec_tbl[0] = kn02xa_io_int;
*imr = 0;
/*
* Setup interrupt structure
*/
dec_interrupt[CLOCK].cpu_mask = IE_IRQ3;
dec_interrupt[CLOCK].iemask = KMIN_CLOCK;
asic_mask_tbl[0] = KMIN_CLOCK;
asic_irq_nr[0] = CLOCK;
dec_interrupt[SCSI_DMA_INT].cpu_mask = IE_IRQ3;
dec_interrupt[SCSI_DMA_INT].iemask = SCSI_DMA_INTS;
asic_mask_tbl[1] = SCSI_DMA_INTS;
asic_irq_nr[1] = SCSI_DMA_INT;
dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ3;
dec_interrupt[SCSI_INT].iemask = SCSI_CHIP;
asic_mask_tbl[2] = SCSI_CHIP;
asic_irq_nr[2] = SCSI_INT;
dec_interrupt[ETHER].cpu_mask = IE_IRQ3;
dec_interrupt[ETHER].iemask = LANCE_INTS;
asic_mask_tbl[3] = LANCE_INTS;
asic_irq_nr[3] = ETHER;
dec_interrupt[SERIAL].cpu_mask = IE_IRQ3;
dec_interrupt[SERIAL].iemask = SERIAL_INTS;
asic_mask_tbl[4] = SERIAL_INTS;
asic_irq_nr[4] = SERIAL;
dec_interrupt[MEMORY].cpu_mask = IE_IRQ3;
dec_interrupt[MEMORY].iemask = KMIN_TIMEOUT;
asic_mask_tbl[5] = KMIN_TIMEOUT;
asic_irq_nr[5] = MEMORY;
dec_interrupt[TC0].cpu_mask = IE_IRQ0;
dec_interrupt[TC0].iemask = 0;
cpu_mask_tbl[1] = IE_IRQ0;
cpu_irq_nr[1] = TC0;
dec_interrupt[TC1].cpu_mask = IE_IRQ1;
dec_interrupt[TC1].iemask = 0;
cpu_mask_tbl[2] = IE_IRQ1;
cpu_irq_nr[2] = TC1;
dec_interrupt[TC2].cpu_mask = IE_IRQ2;
dec_interrupt[TC2].iemask = 0;
cpu_mask_tbl[3] = IE_IRQ2;
cpu_irq_nr[3] = TC2;
dec_interrupt[HALT].cpu_mask = IE_IRQ4;
dec_interrupt[HALT].iemask = 0;
cpu_mask_tbl[4] = IE_IRQ4;
cpu_irq_nr[4] = HALT;
dec_interrupt[FPU].cpu_mask = IE_IRQ5;
dec_interrupt[FPU].iemask = 0;
cpu_mask_tbl[5] = IE_IRQ5;
cpu_irq_nr[5] = FPU;
dec_halt_init(&irq10);
} /* dec_init_kn02ba */
/*
* Machine-specific initialisation for kn02ca, aka maxine, aka DS5000/2x.
*/
void __init dec_init_kn02ca(void)
{
/*
* Setup some memory addresses. FIXME: probably incomplete!
*/
ioasic_base = (void *) KN02XA_IOASIC_BASE;
dec_rtc_base = (char *) KN02XA_RTC_BASE;
isr = (void *) KN02XA_IOASIC_REG(SIR);
imr = (void *) KN02XA_IOASIC_REG(SIMR);
/*
* Setup IOASIC interrupt
*/
cpu_ivec_tbl[1] = kn02xa_io_int;
cpu_irq_nr[1] = -1;
cpu_mask_tbl[1] = IE_IRQ3;
*imr = 0;
/*
* Setup interrupt structure
*/
dec_interrupt[CLOCK].cpu_mask = IE_IRQ1;
dec_interrupt[CLOCK].iemask = 0;
cpu_mask_tbl[0] = IE_IRQ1;
cpu_irq_nr[0] = CLOCK;
dec_interrupt[SCSI_DMA_INT].cpu_mask = IE_IRQ3;
dec_interrupt[SCSI_DMA_INT].iemask = SCSI_DMA_INTS;
asic_mask_tbl[0] = SCSI_DMA_INTS;
asic_irq_nr[0] = SCSI_DMA_INT;
dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ3;
dec_interrupt[SCSI_INT].iemask = SCSI_CHIP;
asic_mask_tbl[1] = SCSI_CHIP;
asic_irq_nr[1] = SCSI_INT;
dec_interrupt[ETHER].cpu_mask = IE_IRQ3;
dec_interrupt[ETHER].iemask = LANCE_INTS;
asic_mask_tbl[2] = LANCE_INTS;
asic_irq_nr[2] = ETHER;
dec_interrupt[SERIAL].cpu_mask = IE_IRQ3;
dec_interrupt[SERIAL].iemask = XINE_SERIAL_INTS;
asic_mask_tbl[3] = XINE_SERIAL_INTS;
asic_irq_nr[3] = SERIAL;
dec_interrupt[TC0].cpu_mask = IE_IRQ3;
dec_interrupt[TC0].iemask = MAXINE_TC0;
asic_mask_tbl[4] = MAXINE_TC0;
asic_irq_nr[4] = TC0;
dec_interrupt[TC1].cpu_mask = IE_IRQ3;
dec_interrupt[TC1].iemask = MAXINE_TC1;
asic_mask_tbl[5] = MAXINE_TC1;
asic_irq_nr[5] = TC1;
dec_interrupt[MEMORY].cpu_mask = IE_IRQ2;
dec_interrupt[MEMORY].iemask = 0;
cpu_mask_tbl[2] = IE_IRQ2;
cpu_irq_nr[2] = MEMORY;
dec_interrupt[HALT].cpu_mask = IE_IRQ4;
dec_interrupt[HALT].iemask = 0;
cpu_mask_tbl[3] = IE_IRQ4;
cpu_irq_nr[3] = HALT;
dec_interrupt[FPU].cpu_mask = IE_IRQ5;
dec_interrupt[FPU].iemask = 0;
cpu_mask_tbl[4] = IE_IRQ5;
cpu_irq_nr[4] = FPU;
dec_halt_init(&irq10);
} /* dec_init_kn02ca */
/*
* Machine-specific initialisation for kn03, aka 3max+, aka DS5000/240.
*/
void __init dec_init_kn03(void)
{
/*
* Setup some memory addresses. FIXME: probably incomplete!
*/
ioasic_base = (void *) KN03_IOASIC_BASE;
dec_rtc_base = (char *) KN03_RTC_BASE;
isr = (void *) KN03_IOASIC_REG(SIR);
imr = (void *) KN03_IOASIC_REG(SIMR);
/*
* Setup IOASIC interrupt
*/
cpu_ivec_tbl[1] = kn03_io_int;
cpu_mask_tbl[1] = IE_IRQ0;
cpu_irq_nr[1] = -1;
*imr = 0;
/*
* Setup interrupt structure
*/
dec_interrupt[CLOCK].cpu_mask = IE_IRQ1;
dec_interrupt[CLOCK].iemask = 0;
cpu_mask_tbl[0] = IE_IRQ1;
cpu_irq_nr[0] = CLOCK;
dec_interrupt[SCSI_DMA_INT].cpu_mask = IE_IRQ0;
dec_interrupt[SCSI_DMA_INT].iemask = SCSI_DMA_INTS;
asic_mask_tbl[0] = SCSI_DMA_INTS;
asic_irq_nr[0] = SCSI_DMA_INT;
dec_interrupt[SCSI_INT].cpu_mask = IE_IRQ0;
dec_interrupt[SCSI_INT].iemask = SCSI_CHIP;
asic_mask_tbl[1] = SCSI_CHIP;
asic_irq_nr[1] = SCSI_INT;
dec_interrupt[ETHER].cpu_mask = IE_IRQ0;
dec_interrupt[ETHER].iemask = LANCE_INTS;
asic_mask_tbl[2] = LANCE_INTS;
asic_irq_nr[2] = ETHER;
dec_interrupt[SERIAL].cpu_mask = IE_IRQ0;
dec_interrupt[SERIAL].iemask = SERIAL_INTS;
asic_mask_tbl[3] = SERIAL_INTS;
asic_irq_nr[3] = SERIAL;
dec_interrupt[TC0].cpu_mask = IE_IRQ0;
dec_interrupt[TC0].iemask = KN03_TC0;
asic_mask_tbl[4] = KN03_TC0;
asic_irq_nr[4] = TC0;
dec_interrupt[TC1].cpu_mask = IE_IRQ0;
dec_interrupt[TC1].iemask = KN03_TC1;
asic_mask_tbl[5] = KN03_TC1;
asic_irq_nr[5] = TC1;
dec_interrupt[TC2].cpu_mask = IE_IRQ0;
dec_interrupt[TC2].iemask = KN03_TC2;
asic_mask_tbl[6] = KN03_TC2;
asic_irq_nr[6] = TC2;
dec_interrupt[MEMORY].cpu_mask = IE_IRQ3;
dec_interrupt[MEMORY].iemask = 0;
cpu_mask_tbl[2] = IE_IRQ3;
cpu_irq_nr[2] = MEMORY;
dec_interrupt[HALT].cpu_mask = IE_IRQ4;
dec_interrupt[HALT].iemask = 0;
cpu_mask_tbl[3] = IE_IRQ4;
cpu_irq_nr[3] = HALT;
dec_interrupt[FPU].cpu_mask = IE_IRQ5;
dec_interrupt[FPU].iemask = 0;
cpu_mask_tbl[4] = IE_IRQ5;
cpu_irq_nr[4] = FPU;
dec_halt_init(&irq10);
} /* dec_init_kn03 */
|
