1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
|
/*
* include/asm-arm/dec21285.h
*
* Copyright (C) 1998 Russell King
*
* DC21285 registers
*/
#define DC21285_PCI_IACK 0x79000000
#define DC21285_ARMCSR_BASE 0x42000000
#define DC21285_PCI_TYPE_0_CONFIG 0x7b000000
#define DC21285_PCI_TYPE_1_CONFIG 0x7a000000
#define DC21285_OUTBOUND_WRITE_FLUSH 0x78000000
#define DC21285_FLASH 0x41000000
#define DC21285_PCI_IO 0x7c000000
#define DC21285_PCI_MEM 0x80000000
#ifndef __ASSEMBLY__
#define DC21285_IO(x) ((volatile unsigned long *)(0xfe000000+(x)))
#else
#define DC21285_IO(x) (x)
#endif
#define CSR_PCICMD DC21285_IO(0x0004)
#define CSR_PCICACHELINESIZE DC21285_IO(0x000c)
#define CSR_PCICSRBASE DC21285_IO(0x0010)
#define CSR_PCICSRIOBASE DC21285_IO(0x0014)
#define CSR_PCISDRAMBASE DC21285_IO(0x0018)
#define CSR_PCIROMBASE DC21285_IO(0x0030)
#define CSR_CSRBASEMASK DC21285_IO(0x00f8)
#define CSR_CSRBASEOFFSET DC21285_IO(0x00fc)
#define CSR_SDRAMBASEMASK DC21285_IO(0x0100)
#define CSR_SDRAMBASEOFFSET DC21285_IO(0x0104)
#define CSR_ROMBASEMASK DC21285_IO(0x0108)
#define CSR_SDRAMTIMING DC21285_IO(0x010c)
#define CSR_SDRAMADDRSIZE0 DC21285_IO(0x0110)
#define CSR_SDRAMADDRSIZE1 DC21285_IO(0x0114)
#define CSR_SDRAMADDRSIZE2 DC21285_IO(0x0118)
#define CSR_SDRAMADDRSIZE3 DC21285_IO(0x011c)
#define CSR_I2O_INFREEHEAD DC21285_IO(0x0120)
#define CSR_I2O_INPOSTTAIL DC21285_IO(0x0124)
#define CSR_I2O_OUTPOSTHEAD DC21285_IO(0x0128)
#define CSR_I2O_OUTFREETAIL DC21285_IO(0x012c)
#define CSR_I2O_INFREECOUNT DC21285_IO(0x0130)
#define CSR_I2O_OUTPOSTCOUNT DC21285_IO(0x0134)
#define CSR_I2O_INPOSTCOUNT DC21285_IO(0x0138)
#define CSR_SA110_CNTL DC21285_IO(0x013c)
#define CSR_PCIADDR_EXTN DC21285_IO(0x0140)
#define CSR_PREFETCHMEMRANGE DC21285_IO(0x0144)
#define CSR_XBUS_CYCLE DC21285_IO(0x0148)
#define CSR_XBUS_IOSTROBE DC21285_IO(0x014c)
#define CSR_DOORBELL_PCI DC21285_IO(0x0150)
#define CSR_DOORBELL_SA110 DC21285_IO(0x0154)
#define CSR_UARTDR DC21285_IO(0x0160)
#define CSR_RXSTAT DC21285_IO(0x0164)
#define CSR_H_UBRLCR DC21285_IO(0x0168)
#define CSR_M_UBRLCR DC21285_IO(0x016c)
#define CSR_L_UBRLCR DC21285_IO(0x0170)
#define CSR_UARTCON DC21285_IO(0x0174)
#define CSR_UARTFLG DC21285_IO(0x0178)
#define CSR_IRQ_STATUS DC21285_IO(0x0180)
#define CSR_IRQ_RAWSTATUS DC21285_IO(0x0184)
#define CSR_IRQ_ENABLE DC21285_IO(0x0188)
#define CSR_IRQ_DISABLE DC21285_IO(0x018c)
#define CSR_IRQ_SOFT DC21285_IO(0x0190)
#define CSR_FIQ_STATUS DC21285_IO(0x0280)
#define CSR_FIQ_RAWSTATUS DC21285_IO(0x0284)
#define CSR_FIQ_ENABLE DC21285_IO(0x0288)
#define CSR_FIQ_DISABLE DC21285_IO(0x028c)
#define CSR_FIQ_SOFT DC21285_IO(0x0290)
#define CSR_TIMER1_LOAD DC21285_IO(0x0300)
#define CSR_TIMER1_VALUE DC21285_IO(0x0304)
#define CSR_TIMER1_CNTL DC21285_IO(0x0308)
#define CSR_TIMER1_CLR DC21285_IO(0x030c)
#define CSR_TIMER2_LOAD DC21285_IO(0x0320)
#define CSR_TIMER2_VALUE DC21285_IO(0x0324)
#define CSR_TIMER2_CNTL DC21285_IO(0x0328)
#define CSR_TIMER2_CLR DC21285_IO(0x032c)
#define CSR_TIMER3_LOAD DC21285_IO(0x0340)
#define CSR_TIMER3_VALUE DC21285_IO(0x0344)
#define CSR_TIMER3_CNTL DC21285_IO(0x0348)
#define CSR_TIMER3_CLR DC21285_IO(0x034c)
#define CSR_TIMER4_LOAD DC21285_IO(0x0360)
#define CSR_TIMER4_VALUE DC21285_IO(0x0364)
#define CSR_TIMER4_CNTL DC21285_IO(0x0368)
#define CSR_TIMER4_CLR DC21285_IO(0x036c)
#define TIMER_CNTL_ENABLE (1 << 7)
#define TIMER_CNTL_AUTORELOAD (1 << 6)
#define TIMER_CNTL_DIV1 (0)
#define TIMER_CNTL_DIV16 (1 << 2)
#define TIMER_CNTL_DIV256 (2 << 2)
#define TIMER_CNTL_CNTEXT (3 << 2)
|
