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<Comment>--------------------------------------------------------------------------------</Comment><br/>
<Comment>-- light52_muldiv.vhdl -- Simple multiplier/divider module.</Comment><br/>
<Comment>--------------------------------------------------------------------------------</Comment><br/>
<Comment>-- The 8051 mul and div instructions are both unsigned and operands are 8 bit.</Comment><br/>
<Comment>--</Comment><br/>
<Comment>-- This module implements the division as a sequential state machine which takes</Comment><br/>
<Comment>-- 8 cycles to complete. </Comment><br/>
<Comment>-- The multiplier can be implemented as sequential or as combinational, in which</Comment><br/>
<Comment>-- case it will use a DSP block in those architectures that support it.</Comment><br/>
<Comment>-- No attempt has been made to make this module generic or reusable.</Comment><br/>
<Comment>--</Comment><br/>
<Comment>-- If you want a combinational multiplier but don't want to waste a DSP block </Comment><br/>
<Comment>-- in this module, you need to modify this file adding whatever synthesis </Comment><br/>
<Comment>-- pragmas your tool of choice needs.</Comment><br/>
<Comment>--</Comment><br/>
<Comment>-- Note that unlike the division state machine, the combinational product logic</Comment><br/>
<Comment>-- is always operating: when SEQUENTIAL_MULTIPLIER=true, prod_out equals </Comment><br/>
<Comment>-- data_a * data_b with a latency of 1 clock cycle, and mul_ready is hardwired</Comment><br/>
<Comment>-- to '1'.</Comment><br/>
<Comment>--</Comment><br/>
<Comment>-- </Comment><Alert Level 2>FIXME</Alert Level 2><Comment> explain division algorithm.</Comment><br/>
<Comment>--------------------------------------------------------------------------------</Comment><br/>
<Comment>-- GENERICS:</Comment><br/>
<Comment>-- </Comment><br/>
<Comment>-- SEQUENTIAL_MULTIPLIER        -- Sequential vs. combinational multiplier.</Comment><br/>
<Comment>--  When true, a sequential implementation will be used for the multiplier, </Comment><br/>
<Comment>--  which will usually save a lot of logic or a dedicated multiplier.</Comment><br/>
<Comment>--  When false, a combinational registered multiplier will be used.</Comment><br/>
<Comment>--</Comment><br/>
<Comment>--------------------------------------------------------------------------------</Comment><br/>
<Comment>-- INTERFACE SIGNALS:</Comment><br/>
<Comment>--</Comment><br/>
<Comment>-- clk :            Clock, active rising edge.</Comment><br/>
<Comment>-- reset :          Synchronous reset. Clears only the control registers not</Comment><br/>
<Comment>--                  visible to the programmer -- not the output registers.</Comment><br/>
<Comment>-- </Comment><br/>
<Comment>-- data_a :         Numerator input, should be connected to the ACC register.</Comment><br/>
<Comment>-- data_b :         Denominator input, should be connected to the B register.</Comment><br/>
<Comment>-- start :          Assert for 1 cycle to start the division state machine</Comment><br/>
<Comment>--                  (and the product if SEQUENTIAL_MULTIPLIER=true);</Comment><br/>
<Comment>-- </Comment><br/>
<Comment>-- prod_out :       Product output, valid only when mul_ready='1'.</Comment><br/>
<Comment>-- quot_out :       Quotient output, valid only when div_ready='1'.</Comment><br/>
<Comment>-- rem_out :        Remainder output, valid only when div_ready='1'.</Comment><br/>
<Comment>-- div_ov_out :     Division overflow flag, valid only when div_ready='1'.</Comment><br/>
<Comment>-- mul_ov_out :     Product overflow flag, valid only when mul_ready='1'.</Comment><br/>
<Comment>-- </Comment><br/>
<Comment>-- mul_ready :      Asserted permanently if SEQUENTIAL_MULTIPLIER=false.</Comment><br/>
<Comment>-- div_ready :      Deasserted the cycle after start is asserted.</Comment><br/>
<Comment>--                  Asserted when the division has completed.</Comment><br/>
<Comment>--</Comment><br/>
<Comment>--------------------------------------------------------------------------------</Comment><br/>
<Comment>-- Copyright (C) 2012 Jose A. Ruiz</Comment><br/>
<Comment>--                                                              </Comment><br/>
<Comment>-- This source file may be used and distributed without         </Comment><br/>
<Comment>-- restriction provided that this copyright statement is not    </Comment><br/>
<Comment>-- removed from the file and that any derivative work contains  </Comment><br/>
<Comment>-- the original copyright notice and the associated disclaimer. </Comment><br/>
<Comment>--                                                              </Comment><br/>
<Comment>-- This source file is free software; you can redistribute it   </Comment><br/>
<Comment>-- and/or modify it under the terms of the GNU Lesser General   </Comment><br/>
<Comment>-- Public License as published by the Free Software Foundation; </Comment><br/>
<Comment>-- either version 2.1 of the License, or (at your option) any   </Comment><br/>
<Comment>-- later version.                                               </Comment><br/>
<Comment>--                                                              </Comment><br/>
<Comment>-- This source is distributed in the hope that it will be       </Comment><br/>
<Comment>-- useful, but WITHOUT ANY WARRANTY; without even the implied   </Comment><br/>
<Comment>-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      </Comment><br/>
<Comment>-- PURPOSE.  See the GNU Lesser General Public License for more </Comment><br/>
<Comment>-- details.                                                     </Comment><br/>
<Comment>--                                                              </Comment><br/>
<Comment>-- You should have received a copy of the GNU Lesser General    </Comment><br/>
<Comment>-- Public License along with this source; if not, download it   </Comment><br/>
<Comment>-- from http://www.opencores.org/lgpl.shtml</Comment><br/>
<Comment>--------------------------------------------------------------------------------</Comment><br/>
<Normal Text></Normal Text><br/>
<Keyword>library</Keyword><Normal Text> ieee;</Normal Text><br/>
<Keyword>use</Keyword><Normal Text> ieee</Normal Text><Operator>.</Operator><Normal Text>std_logic_1164</Normal Text><Operator>.</Operator><Keyword>all</Keyword><Normal Text>;</Normal Text><br/>
<Keyword>use</Keyword><Normal Text> ieee</Normal Text><Operator>.</Operator><Normal Text>numeric_std</Normal Text><Operator>.</Operator><Keyword>all</Keyword><Normal Text>;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Keyword>use</Keyword><Normal Text> work</Normal Text><Operator>.</Operator><Normal Text>light52_pkg</Normal Text><Operator>.</Operator><Keyword>all</Keyword><Normal Text>;</Normal Text><br/>
<Keyword>use</Keyword><Normal Text> work</Normal Text><Operator>.</Operator><Normal Text>light52_ucode_pkg</Normal Text><Operator>.</Operator><Keyword>all</Keyword><Normal Text>;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Control>entity</Control><Normal Text> </Normal Text><Name>light52_muldiv</Name><Normal Text> </Normal Text><Keyword>is</Keyword><br/>
<Normal Text>    </Normal Text><Control>generic</Control><Normal Text> (</Normal Text><br/>
<Normal Text>        SEQUENTIAL_MULTIPLIER </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Data Type>boolean</Data Type><Normal Text> </Normal Text><Operator>:=</Operator><Normal Text> </Normal Text><Keyword>false</Keyword><br/>
<Normal Text>    );</Normal Text><br/>
<Normal Text>    </Normal Text><Control>port</Control><Normal Text>(</Normal Text><br/>
<Normal Text>        clk </Normal Text><Operator>:</Operator><Normal Text>                   </Normal Text><Keyword>in</Keyword><Normal Text> </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>        reset </Normal Text><Operator>:</Operator><Normal Text>                 </Normal Text><Keyword>in</Keyword><Normal Text> </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Normal Text>        data_a </Normal Text><Operator>:</Operator><Normal Text>                </Normal Text><Keyword>in</Keyword><Normal Text> t_byte;</Normal Text><br/>
<Normal Text>        data_b </Normal Text><Operator>:</Operator><Normal Text>                </Normal Text><Keyword>in</Keyword><Normal Text> t_byte;</Normal Text><br/>
<Normal Text>        start </Normal Text><Operator>:</Operator><Normal Text>                 </Normal Text><Keyword>in</Keyword><Normal Text> </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Normal Text>        prod_out </Normal Text><Operator>:</Operator><Normal Text>              </Normal Text><Keyword>out</Keyword><Normal Text> t_word;</Normal Text><br/>
<Normal Text>        quot_out </Normal Text><Operator>:</Operator><Normal Text>              </Normal Text><Keyword>out</Keyword><Normal Text> t_byte;</Normal Text><br/>
<Normal Text>        rem_out </Normal Text><Operator>:</Operator><Normal Text>               </Normal Text><Keyword>out</Keyword><Normal Text> t_byte;</Normal Text><br/>
<Normal Text>        div_ov_out </Normal Text><Operator>:</Operator><Normal Text>            </Normal Text><Keyword>out</Keyword><Normal Text> </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>        mul_ov_out </Normal Text><Operator>:</Operator><Normal Text>            </Normal Text><Keyword>out</Keyword><Normal Text> </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Normal Text>        mul_ready </Normal Text><Operator>:</Operator><Normal Text>             </Normal Text><Keyword>out</Keyword><Normal Text> </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>        div_ready </Normal Text><Operator>:</Operator><Normal Text>             </Normal Text><Keyword>out</Keyword><Normal Text> </Normal Text><Data Type>std_logic</Data Type><br/>
<Normal Text>    );</Normal Text><br/>
<Control>end entity light52_muldiv;</Control><br/>
<Normal Text></Normal Text><br/>
<Control>architecture</Control><Normal Text> </Normal Text><Name>sequential</Name><Normal Text> </Normal Text><Keyword>of</Keyword><Normal Text> </Normal Text><Reference>light52_muldiv</Reference><Normal Text> </Normal Text><Keyword>is</Keyword><br/>
<Normal Text></Normal Text><br/>
<Signal>signal</Signal><Normal Text> bit_ctr </Normal Text><Operator>:</Operator><Normal Text>            </Normal Text><Data Type>integer</Data Type><Normal Text> </Normal Text><Keyword>range</Keyword><Normal Text> </Normal Text><Integer>0</Integer><Normal Text> </Normal Text><Range>to</Range><Normal Text> </Normal Text><Integer>8</Integer><Normal Text>;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Signal>signal</Signal><Normal Text> b_shift_reg </Normal Text><Operator>:</Operator><Normal Text>        t_word;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Signal>signal</Signal><Normal Text> den_ge_256 </Normal Text><Operator>:</Operator><Normal Text>         </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Signal>signal</Signal><Normal Text> num_ge_den </Normal Text><Operator>:</Operator><Normal Text>         </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Signal>signal</Signal><Normal Text> sub_num </Normal Text><Operator>:</Operator><Normal Text>            </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Signal>signal</Signal><Normal Text> denominator </Normal Text><Operator>:</Operator><Normal Text>        t_byte;</Normal Text><br/>
<Signal>signal</Signal><Normal Text> rem_reg </Normal Text><Operator>:</Operator><Normal Text>            t_byte;</Normal Text><br/>
<Signal>signal</Signal><Normal Text> quot_reg </Normal Text><Operator>:</Operator><Normal Text>           t_byte;</Normal Text><br/>
<Signal>signal</Signal><Normal Text> prod_reg </Normal Text><Operator>:</Operator><Normal Text>           t_word;</Normal Text><br/>
<Signal>signal</Signal><Normal Text> ready </Normal Text><Operator>:</Operator><Normal Text>              </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Signal>signal</Signal><Normal Text> load_regs </Normal Text><Operator>:</Operator><Normal Text>          </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Control>begin</Control><br/>
<Normal Text></Normal Text><br/>
<Comment>-- Control logic ---------------------------------------------------------------</Comment><br/>
<Normal Text></Normal Text><br/>
<Name>control_counter</Name><Operator>:</Operator><Normal Text> </Normal Text><Process>process</Process><Normal Text>(clk)</Normal Text><br/>
<Normal Text>    </Normal Text><Keyword>alias</Keyword><Normal Text> sig </Normal Text><Keyword>is</Keyword><Normal Text> </Normal Text><Operator><<</Operator><Signal>signal</Signal><Normal Text> g_test(</Normal Text><Integer>0</Integer><Normal Text>)</Normal Text><Operator>.</Operator><Normal Text>i_test</Normal Text><Operator>.</Operator><Normal Text>sig </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Data Type>std_logic</Data Type><Operator>>></Operator><Normal Text>;</Normal Text><br/>
<Process>begin</Process><br/>
<Normal Text>    </Normal Text><Control>if</Control><Normal Text> clk</Normal Text><Attribute>'event</Attribute><Normal Text> </Normal Text><Keyword>and</Keyword><Normal Text> clk</Normal Text><Operator>=</Operator><Attribute>'1'</Attribute><Normal Text> </Normal Text><Control>then</Control><br/>
<Normal Text>        </Normal Text><Control>if</Control><Normal Text> reset</Normal Text><Operator>=</Operator><Attribute>'1'</Attribute><Normal Text> </Normal Text><Control>then</Control><br/>
<Normal Text>            bit_ctr </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Integer>8</Integer><Normal Text>;</Normal Text><br/>
<Normal Text>        </Normal Text><Control>else</Control><br/>
<Normal Text>            </Normal Text><Control>if</Control><Normal Text> load_regs</Normal Text><Operator>=</Operator><Attribute>'1'</Attribute><Normal Text> </Normal Text><Control>then</Control><br/>
<Normal Text>                bit_ctr </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Integer>0</Integer><Normal Text>;</Normal Text><br/>
<Normal Text>            </Normal Text><Control>elsif</Control><Normal Text> bit_ctr </Normal Text><Operator>/=</Operator><Normal Text> </Normal Text><Integer>8</Integer><Normal Text> </Normal Text><Control>then</Control><br/>
<Normal Text>                bit_ctr </Normal Text><Operator><=</Operator><Normal Text> bit_ctr </Normal Text><Operator>+</Operator><Normal Text> </Normal Text><Integer>1</Integer><Normal Text>;</Normal Text><br/>
<Normal Text>            </Normal Text><Control>end if;</Control><br/>
<Normal Text>        </Normal Text><Control>end if;</Control><br/>
<Normal Text>    </Normal Text><Control>end if;</Control><br/>
<Process>end process control_counter;</Process><br/>
<Normal Text></Normal Text><br/>
<Comment>-- Internal signal ready is asserted after 8 cycles.</Comment><br/>
<Comment>-- The sequential multiplier will use this signal too, IF it takes 8 cycles.</Comment><br/>
<Normal Text></Normal Text><br/>
<Normal Text>ready </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Attribute>'1'</Attribute><Normal Text> </Normal Text><Keyword>when</Keyword><Normal Text> bit_ctr </Normal Text><Operator>>=</Operator><Normal Text> </Normal Text><Integer>8</Integer><Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Attribute>'0'</Attribute><Normal Text>;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Normal Text></Normal Text><br/>
<Comment>---- Divider logic -------------------------------------------------------------</Comment><br/>
<Normal Text></Normal Text><br/>
<Comment>-- What we do is a simple base-2 'shift-and-subtract' algorithm that takes</Comment><br/>
<Comment>-- 8 cycles to complete. We can get away with this because we deal with unsigned</Comment><br/>
<Comment>-- numbers only.</Comment><br/>
<Normal Text></Normal Text><br/>
<Name>divider_registers</Name><Operator>:</Operator><Normal Text> </Normal Text><Process>process</Process><Normal Text>(clk)</Normal Text><br/>
<Process>begin</Process><br/>
<Normal Text>    </Normal Text><Control>if</Control><Normal Text> clk</Normal Text><Attribute>'event</Attribute><Normal Text> </Normal Text><Keyword>and</Keyword><Normal Text> clk</Normal Text><Operator>=</Operator><Attribute>'1'</Attribute><Normal Text> </Normal Text><Control>then</Control><br/>
<Normal Text>        </Normal Text><Comment>-- denominator shift register</Comment><br/>
<Normal Text>        </Normal Text><Control>if</Control><Normal Text> load_regs</Normal Text><Operator>=</Operator><Attribute>'1'</Attribute><Normal Text> </Normal Text><Control>then</Control><br/>
<Normal Text>            b_shift_reg </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Vector>"0"</Vector><Normal Text> </Normal Text><Operator>&</Operator><Normal Text> data_b </Normal Text><Operator>&</Operator><Normal Text> </Normal Text><Vector>"0000000"</Vector><Normal Text>;</Normal Text><br/>
<Normal Text>            </Normal Text><Comment>-- Division overflow can be determined upon loading B reg data.</Comment><br/>
<Normal Text>            </Normal Text><Comment>-- OV will be raised only on div-by-zero.</Comment><br/>
<Normal Text>            </Normal Text><Control>if</Control><Normal Text> data_b</Normal Text><Operator>=</Operator><Normal Text>X</Normal Text><Vector>"00"</Vector><Normal Text> </Normal Text><Control>then</Control><br/>
<Normal Text>                div_ov_out </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Attribute>'1'</Attribute><Normal Text>;</Normal Text><br/>
<Normal Text>            </Normal Text><Control>else</Control><br/>
<Normal Text>                div_ov_out </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Attribute>'0'</Attribute><Normal Text>;</Normal Text><br/>
<Normal Text>            </Normal Text><Control>end if;</Control><br/>
<Normal Text>        </Normal Text><Control>else</Control><br/>
<Normal Text>            b_shift_reg </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Vector>"0"</Vector><Normal Text> </Normal Text><Operator>&</Operator><Normal Text> b_shift_reg(b_shift_reg</Normal Text><Attribute>'high</Attribute><Normal Text> </Normal Text><Range>downto</Range><Normal Text> </Normal Text><Integer>1</Integer><Normal Text>);</Normal Text><br/>
<Normal Text>        </Normal Text><Control>end if;</Control><br/>
<Normal Text>        </Normal Text><br/>
<Normal Text>        </Normal Text><Comment>-- numerator register</Comment><br/>
<Normal Text>        </Normal Text><Control>if</Control><Normal Text> load_regs</Normal Text><Operator>=</Operator><Attribute>'1'</Attribute><Normal Text> </Normal Text><Control>then</Control><Normal Text> </Normal Text><br/>
<Normal Text>            rem_reg </Normal Text><Operator><=</Operator><Normal Text> data_a;</Normal Text><br/>
<Normal Text>        </Normal Text><Control>elsif</Control><Normal Text> bit_ctr</Normal Text><Operator>/=</Operator><Integer>8</Integer><Normal Text> </Normal Text><Keyword>and</Keyword><Normal Text> sub_num</Normal Text><Operator>=</Operator><Attribute>'1'</Attribute><Normal Text> </Normal Text><Control>then</Control><Normal Text> </Normal Text><br/>
<Normal Text>            rem_reg </Normal Text><Operator><=</Operator><Normal Text> rem_reg </Normal Text><Operator>-</Operator><Normal Text> denominator;</Normal Text><br/>
<Normal Text>        </Normal Text><Control>end if;</Control><br/>
<Normal Text></Normal Text><br/>
<Normal Text>        </Normal Text><Comment>--- quotient register</Comment><br/>
<Normal Text>        </Normal Text><Control>if</Control><Normal Text> load_regs</Normal Text><Operator>=</Operator><Attribute>'1'</Attribute><Normal Text> </Normal Text><Control>then</Control><br/>
<Normal Text>            quot_reg </Normal Text><Operator><=</Operator><Normal Text> (</Normal Text><Range>others</Range><Normal Text> </Normal Text><Operator>=></Operator><Normal Text> </Normal Text><Attribute>'0'</Attribute><Normal Text>);</Normal Text><br/>
<Normal Text>        </Normal Text><Control>elsif</Control><Normal Text> bit_ctr</Normal Text><Operator>/=</Operator><Integer>8</Integer><Normal Text> </Normal Text><Control>then</Control><br/>
<Normal Text>            quot_reg </Normal Text><Operator><=</Operator><Normal Text> quot_reg(quot_reg</Normal Text><Attribute>'high-1</Attribute><Normal Text> </Normal Text><Range>downto</Range><Normal Text> </Normal Text><Integer>0</Integer><Normal Text>) </Normal Text><Operator>&</Operator><Normal Text> sub_num;</Normal Text><br/>
<Normal Text>        </Normal Text><Control>end if;</Control><br/>
<Normal Text>        </Normal Text><br/>
<Normal Text>        load_regs </Normal Text><Operator><=</Operator><Normal Text> start;</Normal Text><br/>
<Normal Text>    </Normal Text><Control>end if;</Control><br/>
<Process>end process divider_registers;</Process><br/>
<Normal Text></Normal Text><br/>
<Normal Text>denominator </Normal Text><Operator><=</Operator><Normal Text> b_shift_reg(</Normal Text><Integer>7</Integer><Normal Text> </Normal Text><Range>downto</Range><Normal Text> </Normal Text><Integer>0</Integer><Normal Text>);</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Comment>-- The 16-bit comparison between b_shift_reg (denominator) and the zero-extended </Comment><br/>
<Comment>-- rem_reg (numerator) can be simplified by splitting it in 2: </Comment><br/>
<Comment>-- If the shifted denominator high byte is not zero, it is >=256...</Comment><br/>
<Normal Text>den_ge_256 </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Attribute>'1'</Attribute><Normal Text> </Normal Text><Keyword>when</Keyword><Normal Text> b_shift_reg(</Normal Text><Integer>15</Integer><Normal Text> </Normal Text><Range>downto</Range><Normal Text> </Normal Text><Integer>8</Integer><Normal Text>) </Normal Text><Operator>/=</Operator><Normal Text> X</Normal Text><Vector>"00"</Vector><Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Attribute>'0'</Attribute><Normal Text>;</Normal Text><br/>
<Comment>-- ...otherwise we need to compare the low bytes.</Comment><br/>
<Normal Text>num_ge_den </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Attribute>'1'</Attribute><Normal Text> </Normal Text><Keyword>when</Keyword><Normal Text> rem_reg </Normal Text><Operator>>=</Operator><Normal Text> denominator </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Attribute>'0'</Attribute><Normal Text>;</Normal Text><br/>
<Normal Text>sub_num </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Attribute>'1'</Attribute><Normal Text> </Normal Text><Keyword>when</Keyword><Normal Text> den_ge_256</Normal Text><Operator>=</Operator><Attribute>'0'</Attribute><Normal Text> </Normal Text><Keyword>and</Keyword><Normal Text> num_ge_den</Normal Text><Operator>=</Operator><Attribute>'1'</Attribute><Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Attribute>'0'</Attribute><Normal Text>;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Normal Text></Normal Text><br/>
<Normal Text>quot_out </Normal Text><Operator><=</Operator><Normal Text> quot_reg;</Normal Text><br/>
<Normal Text>prod_out </Normal Text><Operator><=</Operator><Normal Text> prod_reg;</Normal Text><br/>
<Normal Text>rem_out </Normal Text><Operator><=</Operator><Normal Text> rem_reg;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Normal Text>div_ready </Normal Text><Operator><=</Operator><Normal Text> ready;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Comment>---- Multiplier logic ----------------------------------------------------------</Comment><br/>
<Normal Text></Normal Text><br/>
<Comment>---- Combinational multiplier -----------------------------</Comment><br/>
<Name>multiplier_combinational</Name><Operator>:</Operator><Normal Text> </Normal Text><Control>if</Control><Normal Text> </Normal Text><Keyword>not</Keyword><Normal Text> SEQUENTIAL_MULTIPLIER </Normal Text><Control>generate</Control><br/>
<Normal Text></Normal Text><br/>
<Name>registered_combinational_multiplier</Name><Operator>:</Operator><Process>process</Process><Normal Text>(clk)</Normal Text><br/>
<Process>begin</Process><br/>
<Normal Text>    </Normal Text><Control>if</Control><Normal Text> clk</Normal Text><Attribute>'event</Attribute><Normal Text> </Normal Text><Keyword>and</Keyword><Normal Text> clk</Normal Text><Operator>=</Operator><Attribute>'1'</Attribute><Normal Text> </Normal Text><Control>then</Control><br/>
<Normal Text>        prod_reg </Normal Text><Operator><=</Operator><Normal Text> data_a </Normal Text><Operator>*</Operator><Normal Text> data_b; </Normal Text><Comment>-- t_byte is unsigned</Comment><br/>
<Normal Text>    </Normal Text><Control>end if;</Control><br/>
<Process>end process registered_combinational_multiplier;</Process><br/>
<Normal Text></Normal Text><br/>
<Comment>-- The multiplier output is valid in the cycle after the operands are loaded,</Comment><br/>
<Comment>-- so by the time MUL is executed it's already done.</Comment><br/>
<Normal Text>mul_ready </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Attribute>'1'</Attribute><Normal Text>;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Normal Text>mul_ov_out </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Attribute>'1'</Attribute><Normal Text> </Normal Text><Keyword>when</Keyword><Normal Text> prod_reg(</Normal Text><Integer>15</Integer><Normal Text> </Normal Text><Range>downto</Range><Normal Text> </Normal Text><Integer>8</Integer><Normal Text>)</Normal Text><Operator>/=</Operator><Normal Text>X</Normal Text><Vector>"00"</Vector><Normal Text> </Normal Text><Keyword>else</Keyword><Normal Text> </Normal Text><Attribute>'0'</Attribute><Normal Text>;</Normal Text><br/>
<Normal Text>prod_out </Normal Text><Operator><=</Operator><Normal Text> prod_reg;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Control>end generate multiplier_combinational;</Control><br/>
<Normal Text></Normal Text><br/>
<Comment>---- Sequential multiplier --------------------------------</Comment><br/>
<Name>multiplier_sequential</Name><Operator>:</Operator><Normal Text> </Normal Text><Control>if</Control><Normal Text> SEQUENTIAL_MULTIPLIER </Normal Text><Control>generate</Control><br/>
<Normal Text></Normal Text><br/>
<Keyword>assert</Keyword><Normal Text> </Normal Text><Keyword>false</Keyword><br/>
<Keyword>report</Keyword><Normal Text> </Normal Text><Vector>"Sequential multiplier implementation not done yet."</Vector><Operator>&</Operator><br/>
<Normal Text>       </Normal Text><Vector>" Use combinational implementation."</Vector><br/>
<Keyword>severity</Keyword><Normal Text> </Normal Text><Keyword>failure</Keyword><Normal Text>;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Control>end generate multiplier_sequential;</Control><br/>
<Normal Text></Normal Text><br/>
<Control>end sequential;</Control><br/>
<Normal Text></Normal Text><br/>
<Normal Text></Normal Text><br/>
<Keyword>with</Keyword><Normal Text> Types; </Normal Text><Keyword>use</Keyword><Normal Text> Types;</Normal Text><br/>
<Keyword>with</Keyword><Normal Text> Files_Map;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Control>package</Control><Normal Text> </Normal Text><Name>fixed_pkg</Name><Normal Text> </Normal Text><Keyword>is</Keyword><Normal Text> </Normal Text><Keyword>new</Keyword><Normal Text> </Normal Text><Name>IEEE</Name><Operator>.</Operator><Normal Text>fixed_generic_pkg</Normal Text><br/>
<Normal Text>  </Normal Text><Keyword>generic map </Keyword><Normal Text>(</Normal Text><br/>
<Normal Text>    fixed_overflow_style </Normal Text><Operator>=></Operator><Normal Text> IEEE</Normal Text><Operator>.</Operator><Normal Text>fixed_float_types</Normal Text><Operator>.</Operator><Normal Text>fixed_saturate</Normal Text><Operator>,</Operator><br/>
<Normal Text>    fixed_guard_bits     </Normal Text><Operator>=></Operator><Normal Text> </Normal Text><Integer>3</Integer><Operator>,</Operator><br/>
<Normal Text>    no_warning           </Normal Text><Operator>=></Operator><Normal Text> </Normal Text><Keyword>false</Keyword><br/>
<Normal Text>    );</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Control>package</Control><Normal Text> </Normal Text><Name>p</Name><Normal Text> </Normal Text><Keyword>is</Keyword><br/>
<Normal Text>    </Normal Text><Signal>type</Signal><Normal Text> int_ptr </Normal Text><Signal>is</Signal><Normal Text> </Normal Text><Keyword>access</Keyword><Normal Text> </Normal Text><Data Type>integer</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>    </Normal Text><Signal>type</Signal><Normal Text> rec </Normal Text><Signal>is</Signal><Normal Text> </Normal Text><Keyword>record</Keyword><br/>
<Normal Text>        data  </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Data Type>std_logic_vector</Data Type><Normal Text>(</Normal Text><Integer>31</Integer><Normal Text> </Normal Text><Range>downto</Range><Normal Text> </Normal Text><Integer>0</Integer><Normal Text>);</Normal Text><br/>
<Normal Text>        ack   </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>        value </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Data Type>integer</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>        link  </Normal Text><Operator>:</Operator><Normal Text> rec_ptr;</Normal Text><br/>
<Normal Text>    </Normal Text><Keyword>end record;</Keyword><br/>
<Normal Text>    </Normal Text><Signal>type</Signal><Normal Text> int_vec </Normal Text><Signal>is</Signal><Normal Text> </Normal Text><Keyword>array</Keyword><Normal Text> (</Normal Text><Data Type>integer</Data Type><Normal Text> </Normal Text><Keyword>range</Keyword><Normal Text> </Normal Text><Operator><></Operator><Normal Text>) </Normal Text><Keyword>of</Keyword><Normal Text> </Normal Text><Data Type>integer</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>    </Normal Text><Signal>type</Signal><Normal Text> int_vec_ptr </Normal Text><Signal>is</Signal><Normal Text> </Normal Text><Keyword>access</Keyword><Normal Text> int_vec;</Normal Text><br/>
<Normal Text>    </Normal Text><Keyword>procedure</Keyword><Normal Text> </Normal Text><Name>UNIFORM</Name><Normal Text>(</Normal Text><Signal>variable</Signal><Normal Text> SEED1</Normal Text><Operator>,</Operator><Normal Text> SEED2 </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Keyword>inout</Keyword><Normal Text> </Normal Text><Data Type>POSITIVE</Data Type><Normal Text>; </Normal Text><Signal>variable</Signal><Normal Text> X </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Keyword>out</Keyword><Normal Text> </Normal Text><Data Type>REAL</Data Type><Normal Text>);</Normal Text><br/>
<Normal Text>    </Normal Text><Signal>constant</Signal><Normal Text> def_arr </Normal Text><Operator>:</Operator><Normal Text> t_int_array </Normal Text><Operator>:=</Operator><Normal Text> (</Normal Text><Integer>0</Integer><Normal Text> </Normal Text><Range>to</Range><Normal Text> </Normal Text><Integer>2</Integer><Normal Text> </Normal Text><Operator>=></Operator><Normal Text> </Normal Text><Integer>10</Integer><Normal Text>);</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Normal Text>    </Normal Text><Comment>-- type range</Comment><br/>
<Normal Text>    </Normal Text><Signal>type</Signal><Normal Text> newInt </Normal Text><Signal>is</Signal><Normal Text> </Normal Text><Keyword>range</Keyword><Normal Text> </Normal Text><Operator>-</Operator><Integer>4</Integer><Normal Text> </Normal Text><Range>to</Range><Normal Text> </Normal Text><Integer>3</Integer><Normal Text>;</Normal Text><br/>
<Normal Text>    </Normal Text><Signal>type</Signal><Normal Text> CAPACITY </Normal Text><Signal>is</Signal><Normal Text> </Normal Text><Keyword>range</Keyword><Normal Text> </Normal Text><Integer>0</Integer><Normal Text> </Normal Text><Range>to</Range><Normal Text> </Normal Text><Integer>1</Integer><Exponent>E5</Exponent><Normal Text> </Normal Text><Control>units</Control><br/>
<Normal Text>        pF;</Normal Text><br/>
<Normal Text>        nF </Normal Text><Operator>=</Operator><Normal Text> </Normal Text><Integer>1000</Integer><Normal Text> pF;</Normal Text><br/>
<Normal Text>    </Normal Text><Control>end units;</Control><br/>
<Normal Text></Normal Text><br/>
<Normal Text>    </Normal Text><Comment>-- type protected</Comment><br/>
<Normal Text>    </Normal Text><Signal>type</Signal><Normal Text> prot </Normal Text><Signal>is</Signal><Normal Text> </Normal Text><Keyword>protected</Keyword><br/>
<Normal Text>        </Normal Text><Redirection>function</Redirection><Normal Text> </Normal Text><Name>meth</Name><Normal Text>(a </Normal Text><Operator>:</Operator><Normal Text> int) </Normal Text><Control>return</Control><Normal Text> </Normal Text><Data Type>bit</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>    </Normal Text><Keyword>end protected;</Keyword><br/>
<Normal Text></Normal Text><br/>
<Normal Text>    </Normal Text><Comment>-- type protected body</Comment><br/>
<Normal Text>    </Normal Text><Signal>type</Signal><Normal Text> prot </Normal Text><Signal>is</Signal><Normal Text> </Normal Text><Keyword>protected</Keyword><Normal Text> </Normal Text><Keyword>body</Keyword><br/>
<Normal Text>        </Normal Text><Signal>variable</Signal><Normal Text> var </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Data Type>positive</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>        </Normal Text><Signal>constant</Signal><Normal Text> const </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Data Type>boolean</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Normal Text>        </Normal Text><Redirection>function</Redirection><Normal Text> </Normal Text><Name>meth</Name><Normal Text>(a </Normal Text><Operator>:</Operator><Normal Text> int) </Normal Text><Control>return</Control><Normal Text> </Normal Text><Data Type>bit</Data Type><Normal Text> </Normal Text><Keyword>is</Keyword><br/>
<Normal Text>        </Normal Text><Redirection>begin</Redirection><br/>
<Normal Text>        </Normal Text><Redirection>end function;</Redirection><br/>
<Normal Text>    </Normal Text><Keyword>end protected body;</Keyword><br/>
<Normal Text></Normal Text><br/>
<Normal Text>    </Normal Text><Redirection>function</Redirection><Normal Text> </Normal Text><Name>\?=\</Name><Normal Text> (L</Normal Text><Operator>,</Operator><Normal Text> R  </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Data Type>BOOLEAN</Data Type><Normal Text>) </Normal Text><Control>return</Control><Normal Text> </Normal Text><Data Type>BOOLEAN</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Control>end package;</Control><br/>
<Normal Text></Normal Text><br/>
<Control>package</Control><Normal Text> </Normal Text><Control>body</Control><Normal Text> </Normal Text><Name>p</Name><Normal Text> </Normal Text><Keyword>is</Keyword><br/>
<Normal Text>    </Normal Text><Redirection>function</Redirection><Normal Text> </Normal Text><Name>\?=\</Name><Normal Text> (L</Normal Text><Operator>,</Operator><Normal Text> R </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Data Type>BOOLEAN</Data Type><Normal Text>) </Normal Text><Control>return</Control><Normal Text> </Normal Text><Data Type>BOOLEAN</Data Type><Normal Text> </Normal Text><Keyword>is</Keyword><br/>
<Normal Text>    </Normal Text><Redirection>begin</Redirection><br/>
<Normal Text>        </Normal Text><Control>if</Control><Normal Text> </Normal Text><Keyword>not</Keyword><Normal Text> (format(format</Normal Text><Attribute>'left</Attribute><Normal Text>) </Normal Text><Operator>=</Operator><Normal Text> </Normal Text><Attribute>'%'</Attribute><Normal Text>) </Normal Text><Control>then</Control><br/>
<Normal Text>            </Normal Text><Keyword>report</Keyword><Normal Text> </Normal Text><Vector>"to_string: Illegal format string """</Vector><Normal Text> </Normal Text><Operator>&</Operator><Normal Text> format </Normal Text><Operator>&</Operator><Normal Text> </Normal Text><Attribute>'"'</Attribute><br/>
<Normal Text>                </Normal Text><Keyword>severity</Keyword><Normal Text> </Normal Text><Keyword>error</Keyword><Normal Text>;</Normal Text><br/>
<Normal Text>            </Normal Text><Control>return</Control><Normal Text> </Normal Text><Vector>""</Vector><Normal Text>;</Normal Text><br/>
<Normal Text>        </Normal Text><Control>end if;</Control><br/>
<Normal Text>        </Normal Text><Control>return</Control><Normal Text> L </Normal Text><Operator>=</Operator><Normal Text> R;</Normal Text><br/>
<Normal Text>    </Normal Text><Redirection>end function \?=\;</Redirection><br/>
<Normal Text></Normal Text><br/>
<Normal Text>    </Normal Text><Keyword>procedure</Keyword><Normal Text> </Normal Text><Name>test</Name><Normal Text> </Normal Text><Control>is</Control><br/>
<Normal Text>        </Normal Text><Signal>variable</Signal><Normal Text> v </Normal Text><Operator>:</Operator><Normal Text> int_ptr;</Normal Text><br/>
<Normal Text>        </Normal Text><Signal>variable</Signal><Normal Text> i </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Data Type>integer</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>    </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>        v </Normal Text><Operator>:=</Operator><Normal Text> </Normal Text><Keyword>null</Keyword><Normal Text>;</Normal Text><br/>
<Normal Text>        deallocate(v);</Normal Text><br/>
<Normal Text>        v </Normal Text><Operator>:=</Operator><Normal Text> </Normal Text><Keyword>new</Keyword><Normal Text> </Normal Text><Data Type>integer</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>        v </Normal Text><Operator>:=</Operator><Normal Text> </Normal Text><Keyword>new</Keyword><Normal Text> integer</Normal Text><Attribute>'(5)</Attribute><Normal Text>;</Normal Text><br/>
<Normal Text>        v</Normal Text><Operator>.</Operator><Keyword>all</Keyword><Normal Text> </Normal Text><Operator>:=</Operator><Normal Text> </Normal Text><Integer>5</Integer><Normal Text>;</Normal Text><br/>
<Normal Text>        r</Normal Text><Operator>.</Operator><Keyword>all</Keyword><Operator>.</Operator><Normal Text>value </Normal Text><Operator>:=</Operator><Normal Text> </Normal Text><Integer>1</Integer><Normal Text>;</Normal Text><br/>
<Normal Text>        a </Normal Text><Operator>:=</Operator><Normal Text> </Normal Text><Keyword>new</Keyword><Normal Text> int_vec(</Normal Text><Integer>1</Integer><Normal Text> </Normal Text><Range>to</Range><Normal Text> </Normal Text><Integer>3</Integer><Normal Text>);</Normal Text><br/>
<Normal Text>        a</Normal Text><Operator>.</Operator><Keyword>all</Keyword><Normal Text>(</Normal Text><Integer>5</Integer><Normal Text>) </Normal Text><Operator>:=</Operator><Normal Text> </Normal Text><Integer>2</Integer><Normal Text>;</Normal Text><br/>
<Normal Text>        a(</Normal Text><Integer>1</Integer><Normal Text> </Normal Text><Range>to</Range><Normal Text> </Normal Text><Integer>2</Integer><Normal Text>) </Normal Text><Operator>:=</Operator><Normal Text> (</Normal Text><Integer>1</Integer><Operator>,</Operator><Normal Text> </Normal Text><Integer>2</Integer><Normal Text>);</Normal Text><br/>
<Normal Text>        s </Normal Text><Operator>:=</Operator><Normal Text> </Normal Text><Keyword>new</Keyword><Normal Text> string</Normal Text><Attribute>'("")</Attribute><Normal Text>;</Normal Text><br/>
<Normal Text>    </Normal Text><Keyword>end procedure;</Keyword><br/>
<Normal Text></Normal Text><br/>
<Normal Text>    </Normal Text><Keyword>procedure</Keyword><Normal Text> </Normal Text><Name>test2</Name><Normal Text>(x </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Keyword>inout</Keyword><Normal Text> rec_ptr) </Normal Text><Control>is</Control><br/>
<Normal Text>    </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>        x</Normal Text><Operator>.</Operator><Normal Text>value </Normal Text><Operator>:=</Operator><Normal Text> x</Normal Text><Operator>.</Operator><Normal Text>value </Normal Text><Operator>+</Operator><Normal Text> </Normal Text><Integer>1</Integer><Normal Text>;</Normal Text><br/>
<Normal Text>    </Normal Text><Keyword>end procedure;</Keyword><br/>
<Normal Text></Normal Text><br/>
<Normal Text>    </Normal Text><Keyword>procedure</Keyword><Normal Text> </Normal Text><Name>test3</Name><Normal Text> </Normal Text><Control>is</Control><br/>
<Normal Text>        </Normal Text><Signal>type</Signal><Normal Text> a;</Normal Text><br/>
<Normal Text>        </Normal Text><Signal>type</Signal><Normal Text> a </Normal Text><Signal>is</Signal><Normal Text> </Normal Text><Keyword>access</Keyword><Normal Text> </Normal Text><Data Type>integer</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>        </Normal Text><Signal>variable</Signal><Normal Text> v </Normal Text><Operator>:</Operator><Normal Text> a;</Normal Text><br/>
<Normal Text>    </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>    </Normal Text><Keyword>end procedure;</Keyword><br/>
<Normal Text></Normal Text><br/>
<Normal Text>    </Normal Text><Signal>type</Signal><Normal Text> int_ptr_array </Normal Text><Signal>is</Signal><Normal Text> </Normal Text><Keyword>array</Keyword><Normal Text> (</Normal Text><Data Type>integer</Data Type><Normal Text> </Normal Text><Keyword>range</Keyword><Normal Text> </Normal Text><Operator><></Operator><Normal Text>) </Normal Text><Keyword>of</Keyword><Normal Text> int_ptr;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Normal Text>    </Normal Text><Keyword>procedure</Keyword><Normal Text> </Normal Text><Name>tets4</Name><Normal Text> </Normal Text><Control>is</Control><br/>
<Normal Text>        </Normal Text><Signal>type</Signal><Normal Text> bvp </Normal Text><Signal>is</Signal><Normal Text> </Normal Text><Keyword>access</Keyword><Normal Text> </Normal Text><Data Type>bit_vector</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>        </Normal Text><Signal>variable</Signal><Normal Text> y </Normal Text><Operator>:</Operator><Normal Text> int_ptr(</Normal Text><Integer>1</Integer><Normal Text> </Normal Text><Range>to</Range><Normal Text> </Normal Text><Integer>3</Integer><Normal Text>) </Normal Text><Operator>:=</Operator><Normal Text> int_ptr</Normal Text><Attribute>'(null)</Attribute><Normal Text>;</Normal Text><br/>
<Normal Text>    </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>    </Normal Text><Keyword>end procedure;</Keyword><br/>
<Normal Text></Normal Text><br/>
<Normal Text>    </Normal Text><Keyword>procedure</Keyword><Normal Text> </Normal Text><Name>Restore_Origin</Name><Normal Text> (Mark </Normal Text><Operator>:</Operator><Normal Text> Instance_Index_Type) </Normal Text><Control>is</Control><br/>
<Normal Text>    </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>        </Normal Text><Control>for</Control><Normal Text> I </Normal Text><Keyword>in</Keyword><Normal Text> reverse Mark </Normal Text><Operator>+</Operator><Normal Text> </Normal Text><Integer>1</Integer><Normal Text> </Normal Text><Operator>..</Operator><Normal Text> Prev_Instance_Table</Normal Text><Operator>.</Operator><Normal Text>Last </Normal Text><Control>loop</Control><br/>
<Normal Text>            </Normal Text><Keyword>declare</Keyword><br/>
<Normal Text>                El </Normal Text><Operator>:</Operator><Normal Text> Instance_Entry_Type renames Prev_Instance_Table</Normal Text><Operator>.</Operator><Normal Text>Table (I);</Normal Text><br/>
<Normal Text>            </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>                Origin_Table</Normal Text><Operator>.</Operator><Normal Text>Table (El</Normal Text><Operator>.</Operator><Normal Text>N) </Normal Text><Operator>:=</Operator><Normal Text> El</Normal Text><Operator>.</Operator><Normal Text>Old_Origin;</Normal Text><br/>
<Normal Text>            </Normal Text><Keyword>end;</Keyword><br/>
<Normal Text>        </Normal Text><Control>end loop;</Control><br/>
<Normal Text>        Prev_Instance_Table</Normal Text><Operator>.</Operator><Normal Text>Set_Last (Mark);</Normal Text><br/>
<Normal Text>    </Normal Text><Keyword>end Restore_Origin;</Keyword><br/>
<Normal Text></Normal Text><br/>
<Normal Text>    </Normal Text><Comment>--  Instantiate a list.  Simply create a new list and instantiate nodes of</Comment><br/>
<Normal Text>    </Normal Text><Comment>--  that list.</Comment><br/>
<Normal Text>    </Normal Text><Redirection>function</Redirection><Normal Text> </Normal Text><Name>Instantiate_Iir_List</Name><Normal Text> (L </Normal Text><Operator>:</Operator><Normal Text> Iir_List; Is_Ref </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Data Type>Boolean</Data Type><Normal Text>)</Normal Text><br/>
<Normal Text>                                    </Normal Text><Control>return</Control><Normal Text> Iir_List</Normal Text><br/>
<Normal Text>    </Normal Text><Keyword>is</Keyword><br/>
<Normal Text>        Res </Normal Text><Operator>:</Operator><Normal Text> Iir_List;</Normal Text><br/>
<Normal Text>        El </Normal Text><Operator>:</Operator><Normal Text> Iir;</Normal Text><br/>
<Normal Text>    </Normal Text><Redirection>begin</Redirection><br/>
<Normal Text>        </Normal Text><Control>case</Control><Normal Text> to_integer(</Normal Text><Data Type>unsigned</Data Type><Normal Text>(CTRL_REF(x</Normal Text><Operator>*</Operator><Integer>4</Integer><Operator>+</Operator><Integer>3</Integer><Normal Text> </Normal Text><Range>downto</Range><Normal Text> x</Normal Text><Operator>*</Operator><Integer>4</Integer><Normal Text>))) </Normal Text><Keyword>is</Keyword><br/>
<Normal Text>            </Normal Text><Control>when</Control><Normal Text> </Normal Text><Name>Null_Iir_List</Name><br/>
<Normal Text>            </Normal Text><Operator>|</Operator><Normal Text> </Normal Text><Name>Iir_List_All</Name><Normal Text> </Normal Text><Operator>=></Operator><br/>
<Normal Text>                </Normal Text><Control>return</Control><Normal Text> L;</Normal Text><br/>
<Normal Text>            </Normal Text><Control>when</Control><Normal Text> </Normal Text><Keyword>others</Keyword><Normal Text> </Normal Text><Operator>=></Operator><br/>
<Normal Text>                It </Normal Text><Operator>:=</Operator><Normal Text> List_Iterate (L);</Normal Text><br/>
<Normal Text>                </Normal Text><Control>while</Control><Normal Text> Is_Valid (It) </Normal Text><Control>loop</Control><br/>
<Normal Text>                    El </Normal Text><Operator>:=</Operator><Normal Text> Get_Element (It);</Normal Text><br/>
<Normal Text>                    Append_Element (Res</Normal Text><Operator>,</Operator><Normal Text> Instantiate_Iir (El</Normal Text><Operator>,</Operator><Normal Text> Is_Ref));</Normal Text><br/>
<Normal Text>                </Normal Text><Control>end loop;</Control><br/>
<Normal Text>                </Normal Text><Control>for</Control><Normal Text> I </Normal Text><Keyword>in</Keyword><Normal Text> Flist_First </Normal Text><Operator>..</Operator><Normal Text> Flist_Last (L) </Normal Text><Control>loop</Control><br/>
<Normal Text>                    Set_Nth_Element (Res</Normal Text><Operator>,</Operator><Normal Text> I</Normal Text><Operator>,</Operator><Normal Text> Instantiate_Iir (El</Normal Text><Operator>,</Operator><Normal Text> Is_Ref));</Normal Text><br/>
<Normal Text>                </Normal Text><Control>end loop;</Control><br/>
<Normal Text>                </Normal Text><Control>return</Control><Normal Text> Res;</Normal Text><br/>
<Normal Text>        </Normal Text><Control>end case;</Control><br/>
<Normal Text>    </Normal Text><Redirection>end Instantiate_Iir_List;</Redirection><br/>
<Control>end package body;</Control><br/>
<Normal Text></Normal Text><br/>
<Comment>-- Library bar</Comment><br/>
<Keyword>context</Keyword><Normal Text> foo</Normal Text><Operator>.</Operator><Normal Text>test_context;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Keyword>context</Keyword><Normal Text> </Normal Text><Name>foo</Name><Normal Text> </Normal Text><Keyword>is</Keyword><br/>
<Normal Text>    </Normal Text><Keyword>context</Keyword><Normal Text> foo</Normal Text><Operator>.</Operator><Normal Text>test_context;</Normal Text><br/>
<Keyword>end context foo;</Keyword><br/>
<Normal Text></Normal Text><br/>
<Control>entity</Control><Normal Text> </Normal Text><Name>concat</Name><Normal Text> </Normal Text><Keyword>is</Keyword><br/>
<Control>end entity;</Control><br/>
<Normal Text></Normal Text><br/>
<Control>entity</Control><Normal Text> </Normal Text><Name>foo</Name><Normal Text> </Normal Text><Keyword>is</Keyword><br/>
<Normal Text>    </Normal Text><Control>port</Control><Normal Text> (</Normal Text><br/>
<Normal Text>        x </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Keyword>in</Keyword><Normal Text> my_int );</Normal Text><br/>
<Control>end entity;</Control><br/>
<Normal Text></Normal Text><br/>
<Control>architecture</Control><Normal Text> </Normal Text><Name>t</Name><Normal Text> </Normal Text><Keyword>of</Keyword><Normal Text> </Normal Text><Reference>concat</Reference><Normal Text> </Normal Text><Keyword>is</Keyword><br/>
<Normal Text>    </Normal Text><Signal>type</Signal><Normal Text> int_array </Normal Text><Signal>is</Signal><Normal Text> </Normal Text><Keyword>array</Keyword><Normal Text> (</Normal Text><Data Type>integer</Data Type><Normal Text> </Normal Text><Keyword>range</Keyword><Normal Text> </Normal Text><Operator><></Operator><Normal Text>) </Normal Text><Keyword>of</Keyword><Normal Text> </Normal Text><Data Type>integer</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>    </Normal Text><Signal>type</Signal><Normal Text> small </Normal Text><Signal>is</Signal><Normal Text> </Normal Text><Keyword>range</Keyword><Normal Text> </Normal Text><Integer>1</Integer><Normal Text> </Normal Text><Range>to</Range><Normal Text> </Normal Text><Integer>3</Integer><Normal Text>;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Normal Text>    </Normal Text><Control>component</Control><Normal Text> </Normal Text><Name>or_entity</Name><Normal Text> </Normal Text><Keyword>is</Keyword><br/>
<Normal Text>    </Normal Text><Control>port</Control><Normal Text>(</Normal Text><br/>
<Normal Text>        input_1</Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Keyword>in</Keyword><Normal Text> </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>        output</Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Keyword>out</Keyword><Normal Text> </Normal Text><Data Type>std_logic</Data Type><br/>
<Normal Text>        );</Normal Text><br/>
<Normal Text>    </Normal Text><Control>end component;</Control><br/>
<Control>begin</Control><br/>
<Normal Text>    </Normal Text><Process>process</Process><br/>
<Normal Text>        </Normal Text><Signal>variable</Signal><Normal Text> s </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Data Type>string</Data Type><Normal Text>(</Normal Text><Integer>1</Integer><Normal Text> </Normal Text><Range>to</Range><Normal Text> </Normal Text><Integer>5</Integer><Normal Text>);</Normal Text><br/>
<Normal Text>        </Normal Text><Signal>variable</Signal><Normal Text> t </Normal Text><Operator>:</Operator><Normal Text> int_array(</Normal Text><Integer>1</Integer><Normal Text> </Normal Text><Range>to</Range><Normal Text> </Normal Text><Integer>2</Integer><Normal Text>);</Normal Text><br/>
<Normal Text>        </Normal Text><Signal>variable</Signal><Normal Text> c </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Data Type>bit_vector</Data Type><Normal Text>(</Normal Text><Integer>1</Integer><Normal Text> </Normal Text><Range>to</Range><Normal Text> </Normal Text><Integer>4</Integer><Normal Text>);</Normal Text><br/>
<Normal Text>    </Normal Text><Process>begin</Process><br/>
<Normal Text>        x </Normal Text><Operator>:=</Operator><Normal Text> ( </Normal Text><Integer>1</Integer><Operator>,</Operator><Normal Text> </Normal Text><Integer>2</Integer><Operator>,</Operator><Normal Text> </Normal Text><Integer>3</Integer><Normal Text> );</Normal Text><br/>
<Normal Text>        z </Normal Text><Operator>:=</Operator><Normal Text> x </Normal Text><Operator>&</Operator><Normal Text> y;</Normal Text><br/>
<Normal Text>        w </Normal Text><Operator>:=</Operator><Normal Text> </Normal Text><Integer>1</Integer><Normal Text> </Normal Text><Operator>&</Operator><Normal Text> x;</Normal Text><br/>
<Normal Text>        s </Normal Text><Operator>:=</Operator><Normal Text> </Normal Text><Attribute>'h'</Attribute><Normal Text> </Normal Text><Operator>&</Operator><Normal Text> string</Normal Text><Attribute>'("ello")</Attribute><Normal Text>;</Normal Text><br/>
<Normal Text>        </Normal Text><Keyword>assert</Keyword><Normal Text> </Normal Text><Vector>"10"</Vector><Normal Text> </Normal Text><Operator>=</Operator><Normal Text> (b(</Normal Text><Integer>1</Integer><Normal Text>) </Normal Text><Operator>&</Operator><Normal Text> </Normal Text><Vector>"0"</Vector><Normal Text>);</Normal Text><br/>
<Normal Text>        </Normal Text><Keyword>wait</Keyword><Normal Text>;</Normal Text><br/>
<Normal Text>    </Normal Text><Process>end process;</Process><br/>
<Normal Text></Normal Text><br/>
<Normal Text>    </Normal Text><Redirection>function</Redirection><Normal Text> </Normal Text><Name>CounterVal</Name><Normal Text>(Seconds </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Data Type>integer</Data Type><Normal Text> </Normal Text><Operator>:=</Operator><Normal Text> </Normal Text><Integer>0</Integer><Normal Text>) </Normal Text><Control>return</Control><Normal Text> </Normal Text><Data Type>integer</Data Type><Normal Text> </Normal Text><Keyword>is</Keyword><br/>
<Normal Text>        </Normal Text><Signal>variable</Signal><Normal Text> TotalSeconds </Normal Text><Operator>:</Operator><Normal Text> interger;</Normal Text><br/>
<Normal Text>    </Normal Text><Redirection>begin</Redirection><br/>
<Normal Text>        TotalSeconds </Normal Text><Operator>:=</Operator><Normal Text> Seconds </Normal Text><Operator>+</Operator><Normal Text> Minutes </Normal Text><Operator>*</Operator><Normal Text> </Normal Text><Integer>60</Integer><Normal Text>;</Normal Text><br/>
<Normal Text>        </Normal Text><Control>return</Control><Normal Text> TotalSeconds </Normal Text><Operator>*</Operator><Normal Text> ClockFrequencyHz </Normal Text><Operator>-</Operator><Integer>1</Integer><Normal Text>;</Normal Text><br/>
<Normal Text>    </Normal Text><Redirection>end function;</Redirection><br/>
<Normal Text></Normal Text><br/>
<Normal Text>    </Normal Text><Signal>type</Signal><Normal Text> enum_type </Normal Text><Signal>is</Signal><Normal Text> (a</Normal Text><Operator>,</Operator><Normal Text> b</Normal Text><Operator>,</Operator><Normal Text> c</Normal Text><Operator>,</Operator><Normal Text> </Normal Text><Operator>...,</Operator><Normal Text> z);</Normal Text><br/>
<Normal Text>    </Normal Text><Signal>type</Signal><Normal Text> int_array </Normal Text><Signal>is</Signal><Normal Text> </Normal Text><Keyword>array</Keyword><Normal Text>(</Normal Text><Integer>3</Integer><Normal Text> </Normal Text><Range>downto</Range><Normal Text> </Normal Text><Integer>0</Integer><Normal Text>) </Normal Text><Keyword>of</Keyword><Normal Text> </Normal Text><Data Type>integer</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Normal Text>    </Normal Text><Keyword>subtype</Keyword><Normal Text> addr_int </Normal Text><Keyword>is</Keyword><Normal Text> </Normal Text><Data Type>integer</Data Type><Normal Text> </Normal Text><Keyword>range</Keyword><Normal Text> </Normal Text><Integer>0</Integer><Normal Text> </Normal Text><Range>to</Range><Normal Text> </Normal Text><Integer>65535</Integer><Normal Text>;</Normal Text><br/>
<Normal Text>    </Normal Text><Keyword>subtype</Keyword><Normal Text> sub_enum_type </Normal Text><Keyword>is</Keyword><Normal Text> enum_type </Normal Text><Keyword>range</Keyword><Normal Text> a </Normal Text><Range>to</Range><Normal Text> m;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Normal Text>    </Normal Text><Name>inst1</Name><Operator>:</Operator><Normal Text> </Normal Text><Keyword>entity</Keyword><Normal Text> </Normal Text><Reference>work.counter1</Reference><Normal Text>(rtl)</Normal Text><br/>
<Normal Text>        </Normal Text><Keyword>generic map </Keyword><Normal Text>(BITS1 </Normal Text><Operator>=></Operator><Normal Text> </Normal Text><Integer>8</Integer><Normal Text>)</Normal Text><br/>
<Normal Text>        </Normal Text><Keyword>port map </Keyword><Normal Text>(</Normal Text><br/>
<Normal Text>            clk1 </Normal Text><Operator>=></Operator><Normal Text> Clock</Normal Text><Operator>,</Operator><br/>
<Normal Text>            DATA_OUT   </Normal Text><Operator>=></Operator><Normal Text> pwm_data_o(</Normal Text><Integer>3</Integer><Normal Text> </Normal Text><Range>downto</Range><Normal Text> </Normal Text><Integer>5</Integer><Normal Text>)</Normal Text><Operator>,</Operator><br/>
<Normal Text>            COMP_IN(</Normal Text><Integer>1</Integer><Normal Text> </Normal Text><Range>downto</Range><Normal Text> </Normal Text><Integer>0</Integer><Normal Text>)  </Normal Text><Operator>=></Operator><Normal Text> compensate_i</Normal Text><Operator>,</Operator><br/>
<Normal Text>            WRITE_IN   </Normal Text><Operator>=></Operator><Normal Text> (</Normal Text><Range>others</Range><Normal Text> </Normal Text><Operator>=></Operator><Normal Text> </Normal Text><Attribute>'0'</Attribute><Normal Text>)</Normal Text><br/>
<Normal Text>        );</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Normal Text>    </Normal Text><Name>inst2</Name><Operator>:</Operator><Normal Text> </Normal Text><Keyword>component</Keyword><Normal Text> </Normal Text><Reference>counter2</Reference><br/>
<Normal Text>        </Normal Text><Keyword>generic map </Keyword><Normal Text>(BITS1 </Normal Text><Operator>=></Operator><Normal Text> </Normal Text><Integer>8</Integer><Normal Text>)</Normal Text><br/>
<Normal Text>        </Normal Text><Keyword>port map </Keyword><Normal Text>(clk1 </Normal Text><Operator>=></Operator><Normal Text> Clock);</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Normal Text>    </Normal Text><Name>inst3</Name><Operator>:</Operator><Normal Text> </Normal Text><Keyword>configuration</Keyword><Normal Text> </Normal Text><Reference>counter3</Reference><br/>
<Normal Text>        </Normal Text><Keyword>generic map </Keyword><Normal Text>(BITS1 </Normal Text><Operator>=></Operator><Normal Text> </Normal Text><Integer>8</Integer><Normal Text>)</Normal Text><br/>
<Normal Text>        </Normal Text><Keyword>port map </Keyword><Normal Text>(clk1 </Normal Text><Operator>=></Operator><Normal Text> Clock);</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Normal Text>    </Normal Text><Name>THE_PWM_GEN</Name><Normal Text> </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Reference>pwm_generator</Reference><br/>
<Normal Text>        </Normal Text><Keyword>generic map</Keyword><Normal Text>(</Normal Text><br/>
<Normal Text>            dsfds </Normal Text><Operator>=></Operator><Normal Text> ds</Normal Text><br/>
<Normal Text>        )</Normal Text><br/>
<Normal Text>        </Normal Text><Keyword>port map</Keyword><Normal Text>(</Normal Text><br/>
<Normal Text>            CLK        </Normal Text><Operator>=></Operator><Normal Text> clk_i</Normal Text><Operator>,</Operator><br/>
<Normal Text>            DATA_IN    </Normal Text><Operator>=></Operator><Normal Text> pwm_data_i</Normal Text><Operator>,</Operator><br/>
<Normal Text>            DATA_OUT   </Normal Text><Operator>=></Operator><Normal Text> pwm_data_o(</Normal Text><Integer>3</Integer><Normal Text> </Normal Text><Range>downto</Range><Normal Text> </Normal Text><Integer>5</Integer><Normal Text>)</Normal Text><Operator>,</Operator><br/>
<Normal Text>            COMP_IN(</Normal Text><Integer>1</Integer><Normal Text> </Normal Text><Range>downto</Range><Normal Text> </Normal Text><Integer>0</Integer><Normal Text>)  </Normal Text><Operator>=></Operator><Normal Text> compensate_i</Normal Text><Operator>,</Operator><br/>
<Normal Text>            WRITE_IN   </Normal Text><Operator>=></Operator><Normal Text> (</Normal Text><Range>others</Range><Normal Text> </Normal Text><Operator>=></Operator><Normal Text> </Normal Text><Attribute>'0'</Attribute><Normal Text>)</Normal Text><br/>
<Normal Text>        );</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Control>end architecture;</Control><br/>
<Normal Text></Normal Text><br/>
<Control>architecture</Control><Normal Text> </Normal Text><Name>a2</Name><Normal Text> </Normal Text><Keyword>of</Keyword><Normal Text> </Normal Text><Reference>e</Reference><Normal Text> </Normal Text><Keyword>is</Keyword><br/>
<Normal Text>    </Normal Text><Redirection>function</Redirection><Normal Text> </Normal Text><Vector>">"</Vector><Normal Text>(a</Normal Text><Operator>,</Operator><Normal Text> b</Normal Text><Operator>:</Operator><Normal Text> my_int) </Normal Text><Control>return</Control><Normal Text> </Normal Text><Data Type>boolean</Data Type><Normal Text>;</Normal Text><br/>
<Control>begin</Control><br/>
<Normal Text>    </Normal Text><Process>process</Process><Normal Text> </Normal Text><Keyword>is</Keyword><br/>
<Normal Text>        </Normal Text><Signal>variable</Signal><Normal Text> x</Normal Text><Operator>,</Operator><Normal Text> y </Normal Text><Operator>:</Operator><Normal Text> my_int;</Normal Text><br/>
<Normal Text>    </Normal Text><Process>begin</Process><br/>
<Normal Text>        </Normal Text><Keyword>assert</Keyword><Normal Text> x </Normal Text><Operator>></Operator><Normal Text> y;</Normal Text><br/>
<Normal Text>        </Normal Text><Keyword>assert</Keyword><Normal Text> x </Normal Text><Operator><</Operator><Normal Text> y;                   </Normal Text><Comment>-- Error</Comment><br/>
<Normal Text>    </Normal Text><Process>end process;</Process><br/>
<Normal Text></Normal Text><br/>
<Normal Text>    </Normal Text><Name>billowitch_tc586</Name><Operator>:</Operator><Normal Text> </Normal Text><Control>block</Control><Normal Text> </Normal Text><Keyword>is</Keyword><br/>
<Normal Text>        </Normal Text><Signal>type</Signal><Normal Text> real_cons_vector  </Normal Text><Signal>is</Signal><Normal Text> </Normal Text><Keyword>array</Keyword><Normal Text> (</Normal Text><Integer>15</Integer><Normal Text> </Normal Text><Range>downto</Range><Normal Text> </Normal Text><Integer>0</Integer><Normal Text>) </Normal Text><Keyword>of</Keyword><Normal Text> </Normal Text><Data Type>real</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>        </Normal Text><Signal>type</Signal><Normal Text> real_cons_vector_file </Normal Text><Signal>is</Signal><Normal Text> </Normal Text><Keyword>file</Keyword><Normal Text> </Normal Text><Keyword>of</Keyword><Normal Text> real_cons_vector;</Normal Text><br/>
<Normal Text>        </Normal Text><Signal>constant</Signal><Normal Text> C19 </Normal Text><Operator>:</Operator><Normal Text> real_cons_vector </Normal Text><Operator>:=</Operator><Normal Text> (</Normal Text><Range>others</Range><Normal Text> </Normal Text><Operator>=></Operator><Normal Text> </Normal Text><Integer>3</Integer><Operator>.</Operator><Integer>0</Integer><Normal Text>);</Normal Text><br/>
<Normal Text>    </Normal Text><Keyword>begin</Keyword><br/>
<Normal Text>    </Normal Text><Control>end block;</Control><br/>
<Control>end architecture;</Control><br/>
<Normal Text></Normal Text><br/>
<Control>architecture</Control><Normal Text> </Normal Text><Name>arch</Name><Normal Text> </Normal Text><Keyword>of</Keyword><Normal Text> </Normal Text><Reference>ent</Reference><Normal Text> </Normal Text><Keyword>is</Keyword><br/>
<Control>begin</Control><br/>
<Normal Text>  </Normal Text><Name>LL</Name><Operator>:</Operator><Normal Text> </Normal Text><Control>if</Control><Normal Text> test</Normal Text><Operator>=</Operator><Integer>10</Integer><Normal Text> </Normal Text><Control>generate</Control><br/>
<Normal Text>   </Normal Text><Control>begin</Control><br/>
<Normal Text>   </Normal Text><Control>end;</Control><br/>
<Normal Text>  </Normal Text><Control>elsif</Control><Normal Text> test</Normal Text><Operator>=</Operator><Integer>5</Integer><Normal Text> </Normal Text><Control>generate</Control><br/>
<Normal Text>   </Normal Text><Control>begin</Control><br/>
<Normal Text>   </Normal Text><Control>end;</Control><br/>
<Normal Text>  </Normal Text><Control>end generate;</Control><br/>
<Normal Text></Normal Text><br/>
<Normal Text>  </Normal Text><Name>LL</Name><Operator>:</Operator><Normal Text> </Normal Text><Control>if</Control><Normal Text> </Normal Text><Name>l1</Name><Operator>:</Operator><Normal Text> SPEED </Normal Text><Operator>=</Operator><Normal Text> </Normal Text><Vector>"fast"</Vector><Normal Text> </Normal Text><Control>generate</Control><br/>
<Normal Text>  </Normal Text><Control>elsif</Control><Normal Text> test</Normal Text><Operator>=</Operator><Integer>5</Integer><Normal Text> </Normal Text><Control>generate</Control><br/>
<Normal Text>  </Normal Text><Control>end generate;</Control><br/>
<Control>end architecture arch;</Control><br/>
<Normal Text></Normal Text><br/>
<Normal Text></Normal Text><br/>
<Control>architecture</Control><Normal Text> </Normal Text><Name>thing_arch</Name><Normal Text> </Normal Text><Keyword>of</Keyword><Normal Text> </Normal Text><Reference>designthing</Reference><Normal Text> </Normal Text><Keyword>is</Keyword><br/>
<Normal Text></Normal Text><br/>
<Control>component</Control><Normal Text> </Normal Text><Name>pwm_generator</Name><br/>
<Normal Text>  </Normal Text><Control>port</Control><Normal Text>(</Normal Text><br/>
<Normal Text>    CLK        </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Keyword>in</Keyword><Normal Text> </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>    DATA_IN    </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Keyword>in</Keyword><Normal Text>  </Normal Text><Data Type>std_logic_vector</Data Type><Normal Text>(</Normal Text><Integer>15</Integer><Normal Text> </Normal Text><Range>downto</Range><Normal Text> </Normal Text><Integer>0</Integer><Normal Text>);</Normal Text><br/>
<Normal Text>    );</Normal Text><br/>
<Control>end component pwm_generator;</Control><br/>
<Normal Text></Normal Text><br/>
<Signal>attribute</Signal><Normal Text> NOM_FREQ </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Data Type>string</Data Type><Normal Text>;</Normal Text><br/>
<Signal>attribute</Signal><Normal Text> NOM_FREQ </Normal Text><Keyword>of</Keyword><Normal Text> clk_source </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Keyword>label</Keyword><Normal Text> </Normal Text><Keyword>is</Keyword><Normal Text> </Normal Text><Vector>"133.00"</Vector><Normal Text>;</Normal Text><br/>
<Signal>signal</Signal><Normal Text> clk_i  </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text></Normal Text><br/>
<Control>begin</Control><br/>
<Normal Text></Normal Text><br/>
<Name>gen_no_comp</Name><Operator>:</Operator><Normal Text> </Normal Text><Control>if</Control><Normal Text> TEMP </Normal Text><Operator>=</Operator><Normal Text> </Normal Text><Integer>0</Integer><Normal Text> </Normal Text><Control>generate</Control><br/>
<Normal Text>  compensate_i </Normal Text><Operator><=</Operator><Normal Text> (</Normal Text><Range>others</Range><Normal Text> </Normal Text><Operator>=></Operator><Normal Text> </Normal Text><Attribute>'0'</Attribute><Normal Text>);</Normal Text><br/>
<Control>end generate;</Control><br/>
<Normal Text></Normal Text><br/>
<Name>gen_no_comp</Name><Operator>:</Operator><Normal Text> </Normal Text><Control>for</Control><Normal Text> i </Normal Text><Keyword>in</Keyword><Normal Text> </Normal Text><Integer>0</Integer><Normal Text> </Normal Text><Range>to</Range><Normal Text> TEMP </Normal Text><Control>generate</Control><br/>
<Normal Text>  compensate_i </Normal Text><Operator><=</Operator><Normal Text> (</Normal Text><Range>others</Range><Normal Text> </Normal Text><Operator>=></Operator><Normal Text> </Normal Text><Attribute>'0'</Attribute><Normal Text>) </Normal Text><Keyword>after</Keyword><Normal Text> </Normal Text><Integer>10</Integer><Normal Text> </Normal Text><Data Type>ns</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>  compensate_i </Normal Text><Operator><=</Operator><Normal Text> (</Normal Text><Range>others</Range><Normal Text> </Normal Text><Operator>=></Operator><Normal Text> </Normal Text><Attribute>'0'</Attribute><Normal Text>) ;</Normal Text><br/>
<Control>end generate;</Control><br/>
<Normal Text></Normal Text><br/>
<Comment>---------------------------------------------------------------------------</Comment><br/>
<Comment>-- LED blinking when activity on inputs</Comment><br/>
<Comment>---------------------------------------------------------------------------</Comment><br/>
<Name>PROC_TIMER</Name><Normal Text> </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Process>process</Process><Normal Text> </Normal Text><Process>begin</Process><br/>
<Normal Text>  </Normal Text><Keyword>wait</Keyword><Normal Text> </Normal Text><Keyword>until</Keyword><Normal Text> </Normal Text><Keyword>rising_edge</Keyword><Normal Text>(clk_i);</Normal Text><br/>
<Normal Text>  timer </Normal Text><Operator><=</Operator><Normal Text> timer </Normal Text><Operator>+</Operator><Normal Text> </Normal Text><Integer>1</Integer><Normal Text>;</Normal Text><br/>
<Normal Text>  </Normal Text><Keyword>wait</Keyword><Normal Text> </Normal Text><Keyword>for</Keyword><Normal Text> </Normal Text><Integer>10</Integer><Normal Text> </Normal Text><Data Type>ns</Data Type><Normal Text>;</Normal Text><br/>
<Normal Text>  leds </Normal Text><Operator><=</Operator><Normal Text> (last_inp </Normal Text><Keyword>xor</Keyword><Normal Text> inp_status(</Normal Text><Integer>3</Integer><Normal Text> </Normal Text><Range>downto</Range><Normal Text> </Normal Text><Integer>0</Integer><Normal Text>)) </Normal Text><Keyword>or</Keyword><Normal Text> leds </Normal Text><Keyword>or</Keyword><Normal Text> last_leds;</Normal Text><br/>
<Normal Text>  </Normal Text><Control>if</Control><Normal Text> timer </Normal Text><Operator>=</Operator><Normal Text> </Normal Text><Integer>0</Integer><Normal Text> </Normal Text><Control>then</Control><br/>
<Normal Text>    leds </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Keyword>not</Keyword><Normal Text> inp_status(</Normal Text><Integer>3</Integer><Normal Text> </Normal Text><Range>downto</Range><Normal Text> </Normal Text><Integer>0</Integer><Normal Text>);</Normal Text><br/>
<Normal Text>    last_leds </Normal Text><Operator><=</Operator><Normal Text> x</Normal Text><Vector>"0"</Vector><Normal Text>;</Normal Text><br/>
<Normal Text>  </Normal Text><Control>elsif</Control><Normal Text> gf </Normal Text><Control>then</Control><br/>
<Normal Text>    fdsa </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Attribute>'1'</Attribute><Normal Text>;</Normal Text><br/>
<Normal Text>  </Normal Text><Control>end if;</Control><br/>
<Normal Text></Normal Text><br/>
<Normal Text>  </Normal Text><Name>xz</Name><Operator>:</Operator><Normal Text> </Normal Text><Control>for</Control><Normal Text> x </Normal Text><Keyword>in</Keyword><Normal Text> </Normal Text><Integer>0</Integer><Normal Text> </Normal Text><Range>to</Range><Normal Text> </Normal Text><Integer>7</Integer><Normal Text> </Normal Text><Control>loop</Control><br/>
<Normal Text>    dsadf;</Normal Text><br/>
<Normal Text>  </Normal Text><Control>end loop;</Control><br/>
<Normal Text></Normal Text><br/>
<Normal Text>  </Normal Text><Control>case</Control><Normal Text> c </Normal Text><Keyword>is</Keyword><br/>
<Normal Text>    </Normal Text><Control>when</Control><Normal Text> </Normal Text><Name>XXX</Name><Normal Text> </Normal Text><Operator>=></Operator><br/>
<Normal Text>      c </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Integer>1</Integer><Normal Text>;</Normal Text><br/>
<Normal Text>      d </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Integer>21321</Integer><Normal Text>;</Normal Text><br/>
<Normal Text>    </Normal Text><Control>when</Control><Normal Text> </Normal Text><Name>YYYY</Name><Normal Text> </Normal Text><Operator>=></Operator><br/>
<Normal Text>      c </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Integer>2</Integer><Normal Text>;</Normal Text><br/>
<Normal Text>  </Normal Text><Control>end case;</Control><Normal Text> </Normal Text><br/>
<Process>end process;</Process><br/>
<Normal Text></Normal Text><br/>
<Normal Text></Normal Text><br/>
<Name>generate_with_begin</Name><Operator>:</Operator><Normal Text> </Normal Text><Control>if</Control><Normal Text> TEMP </Normal Text><Operator>=</Operator><Normal Text> </Normal Text><Integer>0</Integer><Normal Text> </Normal Text><Control>generate</Control><br/>
<Normal Text>  </Normal Text><Signal>signal</Signal><Normal Text> </Normal Text><Operator>:</Operator><Normal Text> test </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Control>begin</Control><br/>
<Normal Text>  compensate_i </Normal Text><Operator><=</Operator><Normal Text> (</Normal Text><Range>others</Range><Normal Text> </Normal Text><Operator>=></Operator><Normal Text> </Normal Text><Attribute>'0'</Attribute><Normal Text>);</Normal Text><br/>
<Normal Text>  </Normal Text><Control>if</Control><Normal Text> timer </Normal Text><Operator>=</Operator><Normal Text> </Normal Text><Integer>0</Integer><Normal Text> </Normal Text><Control>then</Control><br/>
<Normal Text>    leds </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Keyword>not</Keyword><Normal Text> inp_status(</Normal Text><Integer>3</Integer><Normal Text> </Normal Text><Range>downto</Range><Normal Text> </Normal Text><Integer>0</Integer><Normal Text>);</Normal Text><br/>
<Normal Text>    last_leds </Normal Text><Operator><=</Operator><Normal Text> x</Normal Text><Vector>"0"</Vector><Normal Text>;</Normal Text><br/>
<Normal Text>  </Normal Text><Control>elsif</Control><Normal Text> gf </Normal Text><Control>then</Control><br/>
<Normal Text>    fdsa </Normal Text><Operator><=</Operator><Normal Text> </Normal Text><Attribute>'1'</Attribute><Normal Text>;</Normal Text><br/>
<Normal Text>  </Normal Text><Control>end if;</Control><Normal Text>  </Normal Text><br/>
<Control>end generate generate_with_begin;</Control><br/>
<Normal Text></Normal Text><br/>
<Name>PROC_TIMER</Name><Normal Text> </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Process>process</Process><br/>
<Normal Text>  </Normal Text><Signal>variable</Signal><Normal Text> x </Normal Text><Operator>:</Operator><Normal Text> </Normal Text><Data Type>std_logic</Data Type><Normal Text>;</Normal Text><br/>
<Process>begin</Process><br/>
<Normal Text>  x </Normal Text><Operator>:=</Operator><Normal Text> </Normal Text><Attribute>'0'</Attribute><Normal Text>;</Normal Text><br/>
<Process>end process PROC_TIMER;</Process><br/>
<Normal Text></Normal Text><br/>
<Error>end architecture thing_arc;</Error><Normal Text>   </Normal Text><Comment>--this is not correct (wrong name)</Comment><br/>
<Normal Text></Normal Text><br/>
<Integer>1</Integer><Operator>+</Operator><Integer>1</Integer><br/>
<Integer>2</Integer><Data Type>ns</Data Type><br/>
<Normal Text></Normal Text><br/>
<Integer>1_2_3</Integer><br/>
<Integer>12_3</Integer><br/>
<Integer>1</Integer><Operator>.</Operator><Integer>2</Integer><br/>
<Integer>1</Integer><Operator>.</Operator><Integer>2_3</Integer><br/>
<Integer>1_3</Integer><Operator>.</Operator><Integer>2_3</Integer><br/>
<Integer>12_3</Integer><Exponent>e+1</Exponent><br/>
<Integer>12_3</Integer><Exponent>e-1</Exponent><br/>
<Integer>12_3</Integer><Exponent>e1_1</Exponent><br/>
<Integer>12_3</Integer><Operator>.</Operator><Integer>4</Integer><Exponent>e1_1</Exponent><br/>
<Integer>12_3</Integer><Exponent>e1</Exponent><Normal Text>_</Normal Text><br/>
<Integer>12_3</Integer><Error>e</Error><br/>
<Normal Text></Normal Text><br/>
<Integer>2</Integer><Operator>#</Operator><Based Integer>1_2_3</Based Integer><Operator>#</Operator><Exponent>E+8</Exponent><br/>
<Integer>2</Integer><Operator>#</Operator><Based Integer>1_2</Based Integer><Operator>.</Operator><Based Integer>3</Based Integer><Operator>#</Operator><Exponent>E+8</Exponent><br/>
<Integer>2</Integer><Operator>#</Operator><Based Integer>1_f2</Based Integer><Operator>.</Operator><Based Integer>3</Based Integer><Operator>#</Operator><br/>
<Normal Text></Normal Text><br/>
<Integer>3</Integer><Operator>.</Operator><Integer>14159_26536</Integer><Normal Text> </Normal Text><Comment>-- A literal of type universal_real.</Comment><br/>
<Integer>5280</Integer><Normal Text>          </Normal Text><Comment>-- A literal of type universal_integer.</Comment><br/>
<Integer>10</Integer><Operator>.</Operator><Integer>7</Integer><Normal Text> </Normal Text><Data Type>ns</Data Type><Normal Text>       </Normal Text><Comment>-- A literal of a physical type.</Comment><br/>
<Normal Text>O</Normal Text><Vector>"4777"</Vector><Normal Text>       </Normal Text><Comment>-- A bit string literal.</Comment><br/>
<Vector>"54LS281"</Vector><Normal Text>     </Normal Text><Comment>-- A string literal.</Comment><br/>
<Vector>""</Vector><Normal Text>            </Normal Text><Comment>-- A string literal representing a null array.</Comment><br/>
<Normal Text>B</Normal Text><Vector>"1111_1111_1111"</Vector><Normal Text> </Normal Text><Comment>-- Equivalent to the string literal "111111111111".</Comment><br/>
<Normal Text>X</Normal Text><Vector>"FFF"</Vector><Normal Text>            </Normal Text><Comment>-- Equivalent to B"1111_1111_1111".</Comment><br/>
<Normal Text>O</Normal Text><Vector>"777"</Vector><Normal Text>            </Normal Text><Comment>-- Equivalent to B"111_111_111".</Comment><br/>
<Normal Text>X</Normal Text><Vector>"777"</Vector><Normal Text>            </Normal Text><Comment>-- Equivalent to B"0111_0111_0111".</Comment><br/>
<Normal Text>B</Normal Text><Vector>"XXXX_01LH"</Vector><Normal Text> </Normal Text><Comment>-- Equivalent to the string literal "XXXX01LH"</Comment><br/>
<Normal Text>UO</Normal Text><Vector>"27"</Vector><Normal Text>       </Normal Text><Comment>-- Equivalent to B"010_111"</Comment><br/>
<Normal Text>UO</Normal Text><Vector>"2C"</Vector><Normal Text>       </Normal Text><Comment>-- Equivalent to B"011_CCC"</Comment><br/>
<Normal Text>SX</Normal Text><Vector>"3W"</Vector><Normal Text>       </Normal Text><Comment>-- Equivalent to B"0011_WWWW"</Comment><br/>
<Normal Text>D</Normal Text><Vector>"35"</Vector><Normal Text>        </Normal Text><Comment>-- Equivalent to B"100011"</Comment><br/>
<Integer>12</Integer><Normal Text>UB</Normal Text><Vector>"X1"</Vector><Normal Text> </Normal Text><Comment>-- Equivalent to B"0000_0000_00X1"</Comment><br/>
<Integer>12</Integer><Normal Text>SB</Normal Text><Vector>"X1"</Vector><Normal Text> </Normal Text><Comment>-- Equivalent to B"XXXX_XXXX_XXX1"</Comment><br/>
<Integer>12</Integer><Normal Text>UX</Normal Text><Vector>"F-"</Vector><Normal Text> </Normal Text><Comment>-- Equivalent to B"0000_1111_----"</Comment><br/>
<Integer>12</Integer><Normal Text>SX</Normal Text><Vector>"F-"</Vector><Normal Text> </Normal Text><Comment>-- Equivalent to B"1111_1111_----"</Comment><br/>
<Integer>12</Integer><Normal Text>D</Normal Text><Vector>"13"</Vector><Normal Text>  </Normal Text><Comment>-- Equivalent to B"0000_0000_1101"</Comment><br/>
<Integer>12</Integer><Normal Text>UX</Normal Text><Vector>"000WWW"</Vector><Normal Text> </Normal Text><Comment>-- Equivalent to B"WWWW_WWWW_WWWW"</Comment><br/>
<Integer>12</Integer><Normal Text>SX</Normal Text><Vector>"FFFC00"</Vector><Normal Text> </Normal Text><Comment>-- Equivalent to B"1100_0000_0000"</Comment><br/>
<Integer>12</Integer><Normal Text>SX</Normal Text><Vector>"XXXX00"</Vector><Normal Text> </Normal Text><Comment>-- Equivalent to B"XXXX_0000_0000"</Comment><br/>
<Integer>8</Integer><Normal Text>D</Normal Text><Vector>"511"</Vector><Normal Text>  </Normal Text><Comment>-- Error</Comment><br/>
<Integer>8</Integer><Normal Text>UO</Normal Text><Vector>"477"</Vector><Normal Text> </Normal Text><Comment>-- Error</Comment><br/>
<Integer>8</Integer><Normal Text>SX</Normal Text><Vector>"0FF"</Vector><Normal Text> </Normal Text><Comment>-- Error</Comment><br/>
<Integer>8</Integer><Normal Text>SX</Normal Text><Vector>"FXX"</Vector><Normal Text> </Normal Text><Comment>-- Error</Comment><br/>