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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE language>
<language name="Verilog" version="8" kateversion="5.0" section="Hardware" extensions="*.v;*.V;*.vl" mimetype="text/x-verilog-src" author="Yevgen Voronenko (ysv22@drexel.edu), Ryan Dalzell (ryan@tullyroan.com)" license="">
<highlighting>
<list name="keywords">
<item>macromodule</item>
<item>table</item>
<item>endtable</item>
<item>specify</item>
<item>specparam</item>
<item>endspecify</item>
<item>defparam</item>
<item>default</item>
<item>if</item>
<item>ifnone</item>
<item>else</item>
<item>forever</item>
<item>while</item>
<item>for</item>
<item>wait</item>
<item>repeat</item>
<item>disable</item>
<item>assign</item>
<item>deassign</item>
<item>force</item>
<item>release</item>
<item>always</item>
<item>initial</item>
<item>edge</item>
<item>posedge</item>
<item>negedge</item>
<!-- verilog-2001 keywords -->
<item>config</item>
<item>endconfig</item>
<item>library</item>
<item>design</item>
<item>liblist</item>
<item>cell</item>
<item>use</item>
<item>instance</item>
</list>
<list name="beginwords">
<item>begin</item>
<item>fork</item>
<item>module</item>
<item>case</item>
<item>casex</item>
<item>casez</item>
<item>task</item>
<item>function</item>
<item>generate</item>
</list>
<list name="endwords">
<item>end</item>
<item>join</item>
<item>endmodule</item>
<item>endcase</item>
<item>endtask</item>
<item>endfunction</item>
<item>endgenerate</item>
</list>
<list name="strength">
<!-- drive strength supply0/supply1 omitted, its in types.. -->
<item>strong0</item>
<item>strong1</item>
<item>pull0</item>
<item>pull1</item>
<item>weak0</item>
<item>weak1</item>
<item>highz0</item>
<item>highz1</item>
<!-- charge strength -->
<item>small</item>
<item>medium</item>
<item>large</item>
</list>
<list name="gates">
<item>pullup</item>
<item>pulldown</item>
<item>cmos</item>
<item>rcmos</item>
<item>nmos</item>
<item>pmos</item>
<item>rnmos</item>
<item>rpmos</item>
<item>and</item>
<item>nand</item>
<item>or</item>
<item>nor</item>
<item>xor</item>
<item>xnor</item>
<item>not</item>
<item>buf</item>
<item>tran</item>
<item>rtran</item>
<item>tranif0</item>
<item>tranif1</item>
<item>rtranif0</item>
<item>rtranif1</item>
<item>bufif0</item>
<item>bufif1</item>
<item>notif0</item>
<item>notif1</item>
</list>
<list name="types">
<!-- port direction -->
<item>input</item>
<item>output</item>
<item>inout</item>
<!-- net type -->
<item>wire</item>
<item>tri</item>
<item>tri0</item>
<item>tri1</item>
<item>wand</item>
<item>wor</item>
<item>triand</item>
<item>trior</item>
<item>supply0</item>
<item>supply1</item>
<!-- reg/variable -->
<item>reg</item>
<item>integer</item>
<item>real</item>
<item>realtime</item>
<item>time</item>
<!-- modifier -->
<item>vectored</item>
<item>scalared</item>
<item>trireg</item>
<!-- other -->
<item>parameter</item>
<item>event</item>
<!-- verilog-2001 types -->
<item>signed</item>
<item>automatic</item>
<item>genvar</item>
<item>localparam</item>
</list>
<contexts>
<context attribute="Normal Text" lineEndContext="#stay" name="Normal">
<DetectSpaces />
<RegExpr attribute="Keyword" context="Block name" String="(begin|fork)\ *:" beginRegion="Block"/>
<keyword attribute="Keyword" String="beginwords" context="#stay" beginRegion="Block"/>
<keyword attribute="Keyword" String="endwords" context="#stay" endRegion="Block"/>
<keyword attribute="Keyword" context="#stay" String="keywords" />
<keyword attribute="Data Type" context="#stay" String="types" />
<keyword attribute="Drive/charge strength" context="#stay" String="strength" />
<keyword attribute="Gate instantiation" context="#stay" String="gates" />
<RegExpr attribute="Decimal" context="#stay" String="[\d_]*'d[\d_]+"/>
<RegExpr attribute="Octal" context="#stay" String="[\d_]*'o[0-7xXzZ_]+"/>
<RegExpr attribute="Hex" context="#stay" String="[\d_]*'h[\da-fA-FxXzZ_]+"/>
<RegExpr attribute="Binary" context="#stay" String="[\d_]*'b[01_zZxX]+"/>
<Float attribute="Float" context="#stay"/>
<Int attribute="Integer" context="#stay" />
<RegExpr attribute="Case label" context="#stay" String="[a-zA-Z0-9_, \t]+\s*:" firstNonSpace="true"/>
<!--<RegExpr attribute="Port map" context="Port" String="\.[a-zA-Z0-9_]+"/>-->
<DetectChar attribute="String" context="String" char="""/>
<Detect2Chars attribute="Comment" context="Commentar 1" char="/" char1="/"/>
<Detect2Chars attribute="Comment" context="Commentar 2" char="/" char1="*" beginRegion="Comment"/>
<AnyChar attribute="Symbol" context="#stay" String="!%&()+,-<=+/:;>?[]^{|}~@"/>
<DetectChar attribute="Preprocessor" context="Preprocessor" char="`" column="0"/>
<RegExpr attribute="Preprocessor" context="#stay" String="\`[a-zA-Z_]+\w*" />
<RegExpr attribute="System Task" context="#stay" String="\$[a-zA-Z_]+\w*" />
<RegExpr attribute="Delay" context="#stay" String="#[\d_]+" />
</context>
<context attribute="String" lineEndContext="#pop" name="String">
<LineContinue attribute="String" context="Some Context"/>
<HlCStringChar attribute="String Char" context="#stay"/>
<DetectChar attribute="String" context="#pop" char="""/>
</context>
<context attribute="Comment" lineEndContext="#pop" name="Commentar 1">
<DetectSpaces />
<IncludeRules context="##Comments" />
</context>
<context attribute="Comment" lineEndContext="#stay" name="Commentar 2">
<DetectSpaces />
<Detect2Chars attribute="Comment" context="#pop" char="*" char1="/" endRegion="Comment"/>
<IncludeRules context="##Comments" />
</context>
<context attribute="Preprocessor" lineEndContext="#pop" name="Preprocessor">
<LineContinue attribute="Preprocessor" context="Some Context"/>
<RangeDetect attribute="Prep. Lib" context="#stay" char=""" char1="""/>
<RangeDetect attribute="Prep. Lib" context="#stay" char="<" char1=">"/>
<Detect2Chars attribute="Comment" context="Commentar 1" char="/" char1="/"/>
<Detect2Chars attribute="Comment" context="Commentar/Preprocessor" char="/" char1="*" beginRegion="Comment"/>
</context>
<context attribute="Comment" lineEndContext="#stay" name="Commentar/Preprocessor">
<DetectSpaces />
<Detect2Chars attribute="Comment" context="#pop" char="*" char1="/" endRegion="Comment"/>
<IncludeRules context="##Comments" />
</context>
<context attribute="Normal Text" lineEndContext="#pop" name="Some Context"/>
<context attribute="Block name" lineEndContext="#pop" name="Block name">
<DetectIdentifier attribute="Data Type" context="#pop"/>
</context>
<!-- <context attribute="Normal Text" lineEndContext="#stay" name="Port">
<DetectIdentifier attribute="Normal Text" context="#pop"/>
</context>-->
</contexts>
<itemDatas>
<itemData name="Normal Text" defStyleNum="dsNormal"/>
<itemData name="Keyword" defStyleNum="dsKeyword"/>
<itemData name="Data Type" defStyleNum="dsDataType"/>
<itemData name="Decimal" defStyleNum="dsBaseN"/>
<itemData name="Octal" defStyleNum="dsBaseN"/>
<itemData name="Hex" defStyleNum="dsBaseN"/>
<itemData name="Binary" defStyleNum="dsBaseN"/>
<itemData name="Float" defStyleNum="dsFloat"/>
<itemData name="String" defStyleNum="dsString"/>
<itemData name="String Char" defStyleNum="dsChar"/>
<itemData name="Comment" defStyleNum="dsComment"/>
<itemData name="Symbol" defStyleNum="dsOperator"/>
<itemData name="Preprocessor" defStyleNum="dsOthers"/>
<itemData name="Prep. Lib" defStyleNum="dsFloat"/>
<itemData name="System Task" defStyleNum="dsDataType"/>
<itemData name="Integer" defStyleNum="dsDecVal"/>
<itemData name="Delay" defStyleNum="dsBaseN"/>
<itemData name="Block name" defStyleNum="dsDataType"/>
<itemData name="Drive/charge strength" defStyleNum="dsBaseN"/>
<itemData name="Gate instantiation" defStyleNum="dsDataType"/>
<!-- <itemData name="Port map" defStyleNum="dsDataType"/> -->
<itemData name="Case label" defStyleNum="dsDecVal"/>
</itemDatas>
</highlighting>
<general>
<comments>
<comment name="singleLine" start="//" position="afterwhitespace" />
<comment name="multiLine" start="/*" end="*/" region="Comment"/>
</comments>
<keywords casesensitive="1" />
</general>
</language>
<!-- kate: replace-tabs on; tab-width 2; indent-width 2; -->
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