1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
|
/*-
* Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*
*/
#define ASMC_MAXFANS 6
struct asmc_softc {
device_t sc_dev;
struct mtx sc_mtx;
int sc_nfan;
int16_t sms_rest_x;
int16_t sms_rest_y;
int16_t sms_rest_z;
struct sysctl_oid *sc_fan_tree[ASMC_MAXFANS+1];
struct sysctl_oid *sc_temp_tree;
struct sysctl_oid *sc_sms_tree;
struct sysctl_oid *sc_light_tree;
struct asmc_model *sc_model;
int sc_rid_port;
int sc_rid_irq;
struct resource *sc_ioport;
struct resource *sc_irq;
void *sc_cookie;
int sc_sms_intrtype;
struct taskqueue *sc_sms_tq;
struct task sc_sms_task;
uint8_t sc_sms_intr_works;
};
/*
* Data port.
*/
#define ASMC_DATAPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x00)
#define ASMC_DATAPORT_WRITE(sc, val) \
bus_write_1(sc->sc_ioport, 0x00, val)
#define ASMC_STATUS_MASK 0x0f
/*
* Command port.
*/
#define ASMC_CMDPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x04)
#define ASMC_CMDPORT_WRITE(sc, val) \
bus_write_1(sc->sc_ioport, 0x04, val)
#define ASMC_CMDREAD 0x10
#define ASMC_CMDWRITE 0x11
/*
* Interrupt port.
*/
#define ASMC_INTPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x1f)
/* Number of keys */
#define ASMC_NKEYS "#KEY" /* RO; 4 bytes */
/*
* Fan control via SMC.
*/
#define ASMC_KEY_FANCOUNT "FNum" /* RO; 1 byte */
#define ASMC_KEY_FANMANUAL "FS! " /* RW; 2 bytes */
#define ASMC_KEY_FANID "F%dID" /* RO; 16 bytes */
#define ASMC_KEY_FANSPEED "F%dAc" /* RO; 2 bytes */
#define ASMC_KEY_FANMINSPEED "F%dMn" /* RO; 2 bytes */
#define ASMC_KEY_FANMAXSPEED "F%dMx" /* RO; 2 bytes */
#define ASMC_KEY_FANSAFESPEED "F%dSf" /* RO; 2 bytes */
#define ASMC_KEY_FANTARGETSPEED "F%dTg" /* RW; 2 bytes */
/*
* Sudden Motion Sensor (SMS).
*/
#define ASMC_SMS_INIT1 0xe0
#define ASMC_SMS_INIT2 0xf8
#define ASMC_KEY_SMS "MOCN" /* RW; 2 bytes */
#define ASMC_KEY_SMS_X "MO_X" /* RO; 2 bytes */
#define ASMC_KEY_SMS_Y "MO_Y" /* RO; 2 bytes */
#define ASMC_KEY_SMS_Z "MO_Z" /* RO; 2 bytes */
#define ASMC_KEY_SMS_LOW "MOLT" /* RW; 2 bytes */
#define ASMC_KEY_SMS_HIGH "MOHT" /* RW; 2 bytes */
#define ASMC_KEY_SMS_LOW_INT "MOLD" /* RW; 1 byte */
#define ASMC_KEY_SMS_HIGH_INT "MOHD" /* RW; 1 byte */
#define ASMC_KEY_SMS_FLAG "MSDW" /* RW; 1 byte */
#define ASMC_SMS_INTFF 0x60 /* Free fall Interrupt */
#define ASMC_SMS_INTHA 0x6f /* High Acceleration Interrupt */
#define ASMC_SMS_INTSH 0x80 /* Shock Interrupt */
/*
* Keyboard backlight.
*/
#define ASMC_KEY_LIGHTLEFT "ALV0" /* RO; 6 bytes */
#define ASMC_KEY_LIGHTRIGHT "ALV1" /* RO; 6 bytes */
#define ASMC_KEY_LIGHTVALUE "LKSB" /* WO; 2 bytes */
/*
* Clamshell.
*/
#define ASMC_KEY_CLAMSHELL "MSLD" /* RO; 1 byte */
/*
* Interrupt keys.
*/
#define ASMC_KEY_INTOK "NTOK" /* WO; 1 byte */
/*
* Temperatures.
*
* First for MacBook, second for MacBook Pro, third for Intel Mac Mini,
* fourth the Mac Pro 8-core and finally the MacBook Air.
*
*/
/* maximum array size for temperatures including the last NULL */
#define ASMC_TEMP_MAX 80
#define ASMC_MB_TEMPS { "TB0T", "TN0P", "TN1P", "Th0H", "Th1H", \
"TM0P", NULL }
#define ASMC_MB_TEMPNAMES { "enclosure", "northbridge1", \
"northbridge2", "heatsink1", \
"heatsink2", "memory", }
#define ASMC_MB_TEMPDESCS { "Enclosure Bottomside", \
"Northbridge Point 1", \
"Northbridge Point 2", "Heatsink 1", \
"Heatsink 2", "Memory Bank A", }
#define ASMC_MBP_TEMPS { "TB0T", "Th0H", "Th1H", "Tm0P", \
"TG0H", "TG0P", "TG0T", NULL }
#define ASMC_MBP_TEMPNAMES { "enclosure", "heatsink1", \
"heatsink2", "memory", "graphics", \
"graphicssink", "unknown", }
#define ASMC_MBP_TEMPDESCS { "Enclosure Bottomside", \
"Heatsink 1", "Heatsink 2", \
"Memory Controller", \
"Graphics Chip", "Graphics Heatsink", \
"Unknown", }
#define ASMC_MBP4_TEMPS { "TB0T", "Th0H", "Th1H", "Th2H", "Tm0P", \
"TG0H", "TG0D", "TC0D", "TC0P", "Ts0P", \
"TTF0", "TW0P", NULL }
#define ASMC_MBP4_TEMPNAMES { "enclosure", "heatsink1", "heatsink2", \
"heatsink3", "memory", "graphicssink", \
"graphics", "cpu", "cpu2", "unknown1", \
"unknown2", "wireless", }
#define ASMC_MBP4_TEMPDESCS { "Enclosure Bottomside", \
"Main Heatsink 1", "Main Heatsink 2", \
"Main Heatsink 3", \
"Memory Controller", \
"Graphics Chip Heatsink", \
"Graphics Chip Diode", \
"CPU Temperature Diode", "CPU Point 2", \
"Unknown", "Unknown", \
"Wireless Module", }
#define ASMC_MBP8_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \
"TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
"TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
"TCTD", "TG0D", "TG0P", "THSP", "TM0S", \
"TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \
"Th2H", "Tm0P", "Ts0P", "Ts0S", NULL }
#define ASMC_MBP8_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \
"TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
"TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
"TCTD", "graphics", "TG0P", "THSP", "TM0S", \
"TMBS", "TP0P", "TPCD", "wireless", "Th1H", \
"Th2H", "memory", "Ts0P", "Ts0S" }
#define ASMC_MBP8_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \
"TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
"TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
"TCTD", "TG0D", "TG0P", "THSP", "TM0S", \
"TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \
"Th2H", "Tm0P", "Ts0P", "Ts0S" }
#define ASMC_MBP11_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
"TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
"TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
"TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
"TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
"TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
"TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
"TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
"Ts1S", NULL }
#define ASMC_MBP11_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
"TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
"TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
"TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
"TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
"TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
"TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
"TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
"Ts1S" }
#define ASMC_MBP11_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
"TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
"TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
"TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
"TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
"TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
"TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
"TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
"Ts1S" }
#define ASMC_MM_TEMPS { "TN0P", "TN1P", NULL }
#define ASMC_MM_TEMPNAMES { "northbridge1", "northbridge2" }
#define ASMC_MM_TEMPDESCS { "Northbridge Point 1", \
"Northbridge Point 2" }
#define ASMC_MM31_TEMPS { "TC0D", "TC0H", \
"TC0P", "TH0P", \
"TN0D", "TN0P", \
"TW0P", NULL }
#define ASMC_MM31_TEMPNAMES { "cpu0_die", "cpu0_heatsink", \
"cpu0_proximity", "hdd_bay", \
"northbridge_die", \
"northbridge_proximity", \
"wireless_module", }
#define ASMC_MM31_TEMPDESCS { "CPU0 Die Core Temperature", \
"CPU0 Heatsink Temperature", \
"CPU0 Proximity Temperature", \
"HDD Bay Temperature", \
"Northbridge Die Core Temperature", \
"Northbridge Proximity Temperature", \
"Wireless Module Temperature", }
#define ASMC_MP_TEMPS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
"TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
"TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
"TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
"TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
"TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
"TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \
NULL }
#define ASMC_MP_TEMPNAMES { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
"TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
"TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
"TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
"TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
"TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
"TM8S", "TM9P", "TM9S", "TN0H", "TS0C", }
#define ASMC_MP_TEMPDESCS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
"TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
"TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
"TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
"TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
"TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
"TM8S", "TM9P", "TM9S", "TN0H", "TS0C", }
#define ASMC_MP5_TEMPS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \
"TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
"TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
"TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
"TH4F", "TH4P", "TH4V", "THPS", "THTG", \
"TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
"TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
"TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \
"TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \
"TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \
"TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
"Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
"Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
"Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
"TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", \
NULL }
#define ASMC_MP5_TEMPNAMES { "ambient", "TCAC", "TCAD", "TCAG", "TCAH", \
"TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
"TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
"TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
"TH4F", "TH4P", "TH4V", "THPS", "THTG", \
"TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
"TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
"TM7V", "TM8P", "TM8V", "TM9V", "ram_a1", \
"ram_a2", "ram_a3", "ram_a4", "ram_b1", "ram_b2", \
"ram_b3", "ram_b4", "TMHS", "TMLS", "TMPS", \
"TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
"Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
"Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
"Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
"TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", }
#define ASMC_MP5_TEMPDESCS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \
"TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
"TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
"TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
"TH4F", "TH4P", "TH4V", "THPS", "THTG", \
"TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
"TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
"TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \
"TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \
"TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \
"TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
"Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
"Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
"Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
"TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", }
#define ASMC_MBA_TEMPS { "TB0T", NULL }
#define ASMC_MBA_TEMPNAMES { "enclosure" }
#define ASMC_MBA_TEMPDESCS { "Enclosure Bottom" }
#define ASMC_MBA3_TEMPS { "TB0T", "TB1T", "TB2T", \
"TC0D", "TC0E", "TC0P", NULL }
#define ASMC_MBA3_TEMPNAMES { "enclosure", "TB1T", "TB2T", \
"TC0D", "TC0E", "TC0P" }
#define ASMC_MBA3_TEMPDESCS { "Enclosure Bottom", "TB1T", "TB2T", \
"TC0D", "TC0E", "TC0P" }
|
