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|
<!-- Creator : groff version 1.22.4 -->
<!-- CreationDate: Sun May 29 15:04:59 2022 -->
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<title>lepton-netlist</title>
</head>
<body>
<h1 align="center">lepton-netlist</h1>
<a href="#NAME">NAME</a><br>
<a href="#SYNOPSIS">SYNOPSIS</a><br>
<a href="#DESCRIPTION">DESCRIPTION</a><br>
<a href="#GENERAL OPTIONS">GENERAL OPTIONS</a><br>
<a href="#BACKENDS">BACKENDS</a><br>
<a href="#EXAMPLES">EXAMPLES</a><br>
<a href="#AUTHORS">AUTHORS</a><br>
<a href="#COPYRIGHT">COPYRIGHT</a><br>
<a href="#SEE ALSO">SEE ALSO</a><br>
<hr>
<h2>NAME
<a name="NAME"></a>
</h2>
<p style="margin-left:11%; margin-top: 1em">lepton-netlist
- Lepton EDA Netlist Extraction and Generation</p>
<h2>SYNOPSIS
<a name="SYNOPSIS"></a>
</h2>
<p style="margin-left:11%; margin-top: 1em"><b>lepton-netlist</b>
[<i>OPTION</i> ...] [<b>-g</b> <i>BACKEND</i> | <b>-f</b>
<i>FILE</i>] [<i>--</i>] <i>FILE</i> ...</p>
<h2>DESCRIPTION
<a name="DESCRIPTION"></a>
</h2>
<p style="margin-left:11%; margin-top: 1em"><b>lepton-netlist</b>
is a netlist extraction and generation tool, and is part of
the Lepton EDA (Electronic Design Automation) toolset. It
takes one or more electronic schematics as input, and
outputs a netlist. A netlist is a machine-interpretable
description of the way that components in an electronic
circuit are connected together, and is commonly used as the
input to a PCB layout program such as <b>pcb</b>(1) or to a
simulator such as <b>gnucap</b>(1).</p>
<p style="margin-left:11%; margin-top: 1em">A normal
<b>lepton-netlist</b> run is carried out in two steps.
First, the <b>lepton-netlist</b> frontend loads the
specified human-readable schematic <i>FILE</i>s, and
compiles them to an in-memory netlist description. Next, a
’backend’ is used to export the connection and
component data to one of many supported netlist formats.</p>
<p style="margin-left:11%; margin-top: 1em"><b>lepton-netlist</b>
is extensible, using the Scheme programming language.</p>
<h2>GENERAL OPTIONS
<a name="GENERAL OPTIONS"></a>
</h2>
<table width="100%" border="0" rules="none" frame="void"
cellspacing="0" cellpadding="0">
<tr valign="top" align="left">
<td width="11%"></td>
<td width="3%">
<p style="margin-top: 1em"><b>-q</b></p></td>
<td width="9%"></td>
<td width="77%">
<p style="margin-top: 1em">Quiet mode. Turns off all
warnings/notes/messages.</p> </td></tr>
</table>
<p style="margin-left:11%;"><b>-v</b>, <b>--verbose</b></p>
<p style="margin-left:23%;">Verbose mode. Output all
diagnostic information.</p>
<p style="margin-left:11%;"><b>-L</b> <i>DIRECTORY</i></p>
<p style="margin-left:23%;">Prepend <i>DIRECTORY</i> to the
list of directories to be searched for Scheme files.</p>
<p style="margin-left:11%;"><b>-g</b> <i>BACKEND</i></p>
<p style="margin-left:23%;">Specify the netlist backend to
be used.</p>
<table width="100%" border="0" rules="none" frame="void"
cellspacing="0" cellpadding="0">
<tr valign="top" align="left">
<td width="11%"></td>
<td width="11%">
<p><b>-f</b> <i>FILE</i></p></td>
<td width="1%"></td>
<td width="77%">
<p>Load and use netlist backend from <i>FILE</i>.
<i>FILE</i> is expected to have name like
"gnet-NAME.scm" and contain entry point function
NAME (where NAME is the backend’s name).</p></td></tr>
</table>
<p style="margin-left:11%;"><b>-O</b> <i>STRING</i></p>
<p style="margin-left:23%;">Pass an option string to the
backend.</p>
<p style="margin-left:11%;"><b>-b</b>,
<b>--list-backends</b></p>
<p style="margin-left:23%;">Print a list of available
netlist backends.</p>
<table width="100%" border="0" rules="none" frame="void"
cellspacing="0" cellpadding="0">
<tr valign="top" align="left">
<td width="11%"></td>
<td width="11%">
<p><b>-o</b> <i>FILE</i></p></td>
<td width="1%"></td>
<td width="77%">
<p>Specify the filename for the generated netlist. By
default, output is directed to ’output.net’. If
’-’ is given instead of a filename, the output
is directed to the standard output.</p></td></tr>
<tr valign="top" align="left">
<td width="11%"></td>
<td width="11%">
<p><b>-l</b> <i>FILE</i></p></td>
<td width="1%"></td>
<td width="77%">
<p>Specify a Scheme file to be loaded before the backend is
loaded or executed. This option can be specified multiple
times.</p> </td></tr>
<tr valign="top" align="left">
<td width="11%"></td>
<td width="11%">
<p><b>-m</b> <i>FILE</i></p></td>
<td width="1%"></td>
<td width="77%">
<p>Specify a Scheme file to be loaded between loading the
backend and executing it. This option can be specified
multiple times.</p></td></tr>
<tr valign="top" align="left">
<td width="11%"></td>
<td width="11%">
<p><b>-c</b> <i>EXPR</i></p></td>
<td width="1%"></td>
<td width="77%">
<p>Specify a Scheme expression to be executed during
<b>lepton-netlist</b> startup. This option can be specified
multiple times.</p></td></tr>
<tr valign="top" align="left">
<td width="11%"></td>
<td width="11%">
<p><b>-i</b></p></td>
<td width="1%"></td>
<td width="77%">
<p>After the schematic files have been loaded and compiled,
and after all Scheme files have been loaded, but before
running the backend, enter a Scheme read-eval-print
loop.</p> </td></tr>
</table>
<p style="margin-left:11%;"><b>-h</b>, <b>--help</b></p>
<p style="margin-left:23%;">Print a help message.</p>
<p style="margin-left:11%;"><b>-V</b>, <b>--version</b></p>
<p style="margin-left:23%;">Print <b>lepton-netlist</b>
version information.</p>
<table width="100%" border="0" rules="none" frame="void"
cellspacing="0" cellpadding="0">
<tr valign="top" align="left">
<td width="11%"></td>
<td width="3%">
<p><b>--</b></p></td>
<td width="9%"></td>
<td width="77%">
<p>Treat all remaining arguments as schematic filenames.
Use this if you have a schematic filename which begins with
’-’.</p> </td></tr>
</table>
<h2>BACKENDS
<a name="BACKENDS"></a>
</h2>
<p style="margin-left:11%; margin-top: 1em">Currently,
<b>lepton-netlist</b> includes the following backends:</p>
<table width="100%" border="0" rules="none" frame="void"
cellspacing="0" cellpadding="0">
<tr valign="top" align="left">
<td width="11%"></td>
<td width="11%">
<p style="margin-top: 1em"><b>allegro</b></p></td>
<td width="1%"></td>
<td width="55%">
<p style="margin-top: 1em">Allegro netlist format.</p></td>
<td width="22%">
</td></tr>
<tr valign="top" align="left">
<td width="11%"></td>
<td width="11%">
<p><b>bae</b></p></td>
<td width="1%"></td>
<td width="55%">
<p>Bartels Autoengineer netlist format.</p></td>
<td width="22%">
</td></tr>
</table>
<p style="margin-left:11%;"><b>bom</b>, <b>bom2</b></p>
<p style="margin-left:23%;">Bill of materials
generation.</p>
<table width="100%" border="0" rules="none" frame="void"
cellspacing="0" cellpadding="0">
<tr valign="top" align="left">
<td width="11%"></td>
<td width="11%">
<p><b>calay</b></p></td>
<td width="1%"></td>
<td width="39%">
<p>Calay netlist format.</p></td>
<td width="38%">
</td></tr>
<tr valign="top" align="left">
<td width="11%"></td>
<td width="11%">
<p><b>cascade</b></p></td>
<td width="1%"></td>
<td width="39%">
<p>RF Cascade netlist format</p></td>
<td width="38%">
</td></tr>
</table>
<p style="margin-left:11%;"><b>drc</b>, <b>drc2</b></p>
<p style="margin-left:23%;">Design rule checkers
(<b>drc2</b> is recommended).</p>
<table width="100%" border="0" rules="none" frame="void"
cellspacing="0" cellpadding="0">
<tr valign="top" align="left">
<td width="11%"></td>
<td width="7%">
<p><b>eagle</b></p></td>
<td width="5%"></td>
<td width="77%">
<p>Eagle netlist format.</p></td></tr>
<tr valign="top" align="left">
<td width="11%"></td>
<td width="7%">
<p><b>ewnet</b></p></td>
<td width="5%"></td>
<td width="77%">
<p>Netlist format for National Instruments ULTIboard layout
tool.</p> </td></tr>
</table>
<p style="margin-left:11%;"><b>futurenet2</b></p>
<p style="margin-left:23%;">Futurenet2 netlist format.</p>
<table width="100%" border="0" rules="none" frame="void"
cellspacing="0" cellpadding="0">
<tr valign="top" align="left">
<td width="11%"></td>
<td width="9%">
<p><b>geda</b></p></td>
<td width="3%"></td>
<td width="77%">
<p>Native gEDA netlist format (mainly used for testing and
diagnostics).</p> </td></tr>
<tr valign="top" align="left">
<td width="11%"></td>
<td width="9%">
<p><b>gossip</b></p></td>
<td width="3%"></td>
<td width="77%">
<p>Gossip netlist format.</p></td></tr>
</table>
<p style="margin-left:11%;"><b>gsch2pcb</b></p>
<p style="margin-left:23%;">Backend used for <b>pcb</b>(1)
file layout generation by <b>gsch2pcb</b>(1). It is not
recommended to use this backend directly.</p>
<p style="margin-left:11%;"><b>liquidpcb</b></p>
<p style="margin-left:23%;">LiquidPCB netlist format.</p>
<p style="margin-left:11%;"><b>mathematica</b></p>
<p style="margin-left:23%;">Netlister for analytical
circuit solving using Mathematica.</p>
<p style="margin-left:11%;"><b>maxascii</b></p>
<p style="margin-left:23%;">MAXASCII netlist format.</p>
<table width="100%" border="0" rules="none" frame="void"
cellspacing="0" cellpadding="0">
<tr valign="top" align="left">
<td width="11%"></td>
<td width="9%">
<p><b>osmond</b></p></td>
<td width="3%"></td>
<td width="34%">
<p>Osmond netlist format.</p></td>
<td width="43%">
</td></tr>
<tr valign="top" align="left">
<td width="11%"></td>
<td width="9%">
<p><b>pads</b></p></td>
<td width="3%"></td>
<td width="34%">
<p>PADS netlist format.</p></td>
<td width="43%">
</td></tr>
</table>
<p style="margin-left:11%;"><b>partslist1</b>,
<b>partslist2</b>, <b>partslist3</b></p>
<p style="margin-left:23%;">Bill of materials generation
backends (alternatives to <b>bom</b> and <b>bom2</b>).</p>
<table width="100%" border="0" rules="none" frame="void"
cellspacing="0" cellpadding="0">
<tr valign="top" align="left">
<td width="11%"></td>
<td width="11%">
<p><b>PCB</b></p></td>
<td width="1%"></td>
<td width="77%">
<p><b>pcb</b>(1) netlist format.</p></td></tr>
<tr valign="top" align="left">
<td width="11%"></td>
<td width="11%">
<p><b>pcbpins</b></p></td>
<td width="1%"></td>
<td width="77%">
<p>Generates a <b>pcb</b>(1) action file for forward
annotating pin/pad names from schematic to layout.</p></td></tr>
</table>
<p style="margin-left:11%;"><b>protelII</b></p>
<p style="margin-left:23%;">Protel II netlist format.</p>
<table width="100%" border="0" rules="none" frame="void"
cellspacing="0" cellpadding="0">
<tr valign="top" align="left">
<td width="11%"></td>
<td width="7%">
<p><b>redac</b></p></td>
<td width="5%"></td>
<td width="42%">
<p>RACAL-REDAC netlist format.</p></td>
<td width="35%">
</td></tr>
</table>
<p style="margin-left:11%;"><b>spice</b>,
<b>spice-sdb</b></p>
<p style="margin-left:23%;">SPICE-compatible netlist format
(<b>spice-sdb</b> is recommended). Suitable for use with
<b>gnucap</b>(1).</p>
<table width="100%" border="0" rules="none" frame="void"
cellspacing="0" cellpadding="0">
<tr valign="top" align="left">
<td width="11%"></td>
<td width="11%">
<p><b>switcap</b></p></td>
<td width="1%"></td>
<td width="77%">
<p>SWITCAP switched capacitor simulator netlist format.</p></td></tr>
<tr valign="top" align="left">
<td width="11%"></td>
<td width="11%">
<p><b>systemc</b></p></td>
<td width="1%"></td>
<td width="77%">
<p>Structural SystemC code generation.</p></td></tr>
<tr valign="top" align="left">
<td width="11%"></td>
<td width="11%">
<p><b>tango</b></p></td>
<td width="1%"></td>
<td width="77%">
<p>Tango netlist format.</p></td></tr>
<tr valign="top" align="left">
<td width="11%"></td>
<td width="11%">
<p><b>tEDAx</b></p></td>
<td width="1%"></td>
<td width="77%">
<p>Trivial EDA eXchange (tEDAx) format.</p></td></tr>
<tr valign="top" align="left">
<td width="11%"></td>
<td width="11%">
<p><b>vams</b></p></td>
<td width="1%"></td>
<td width="77%">
<p>VHDL-AMS code generation.</p></td></tr>
<tr valign="top" align="left">
<td width="11%"></td>
<td width="11%">
<p><b>verilog</b></p></td>
<td width="1%"></td>
<td width="77%">
<p>Verilog code generation.</p></td></tr>
<tr valign="top" align="left">
<td width="11%"></td>
<td width="11%">
<p><b>vhdl</b></p></td>
<td width="1%"></td>
<td width="77%">
<p>VHDL code generation.</p></td></tr>
<tr valign="top" align="left">
<td width="11%"></td>
<td width="11%">
<p><b>vipec</b></p></td>
<td width="1%"></td>
<td width="77%">
<p>ViPEC Network Analyser netlist format.</p></td></tr>
</table>
<h2>EXAMPLES
<a name="EXAMPLES"></a>
</h2>
<p style="margin-left:11%; margin-top: 1em">These examples
assume that you have a ’stack_1.sch’ in the
current directory.</p>
<p style="margin-left:11%; margin-top: 1em"><b>lepton-netlist</b>
requires that at least one schematic to be specified on the
command line:</p>
<p style="margin-left:11%; margin-top: 1em">./lepton-netlist
stack_1.sch</p>
<p style="margin-left:11%; margin-top: 1em">This is not
very useful since it does not direct <b>lepton-netlist</b>
to do <br>
anything.</p>
<p style="margin-left:11%; margin-top: 1em">Specify a
backend name with ’-g’ to get
<b>lepton-netlist</b> to output a <br>
netlist:</p>
<table width="100%" border="0" rules="none" frame="void"
cellspacing="0" cellpadding="0">
<tr valign="top" align="left">
<td width="8%"></td>
<td width="92%">
<p>./lepton-netlist -g geda stack_1.sch</p></td></tr>
</table>
<p style="margin-left:11%; margin-top: 1em">The netlist
output will be written to a file called
’output.net’ <br>
in the current working directory.</p>
<p style="margin-left:11%; margin-top: 1em">You can specify
the output filename by using the ’-o’
option:</p>
<table width="100%" border="0" rules="none" frame="void"
cellspacing="0" cellpadding="0">
<tr valign="top" align="left">
<td width="8%"></td>
<td width="92%">
<p>./lepton-netlist -g geda stack_1.sch -o
/tmp/stack.netlist</p> </td></tr>
</table>
<p style="margin-left:11%; margin-top: 1em">Output will now
be directed to ’/tmp/stack.netlist’.</p>
<p style="margin-left:11%; margin-top: 1em">You could run
(for example) the ’spice-sdb’ backend against
the <br>
schematic if you specified ’-g spice-sdb’, or
you could generate a <br>
bill of materials for the schematic using ’-g
partslist1’.</p>
<p style="margin-left:11%; margin-top: 1em">To obtain a
Scheme prompt to run Scheme expressions directly, you can
<br>
use the ’-i’ option.</p>
<table width="100%" border="0" rules="none" frame="void"
cellspacing="0" cellpadding="0">
<tr valign="top" align="left">
<td width="8%"></td>
<td width="92%">
<p>./lepton-netlist -i stack_1.sch</p></td></tr>
</table>
<p style="margin-left:11%; margin-top: 1em"><b>lepton-netlist</b>
will load ’stack_1.sh’, and then enter an
interactive <br>
Scheme read-eval-print loop.</p>
<h2>AUTHORS
<a name="AUTHORS"></a>
</h2>
<p style="margin-left:11%; margin-top: 1em">See the
’AUTHORS’ file included with this program.</p>
<h2>COPYRIGHT
<a name="COPYRIGHT"></a>
</h2>
<p style="margin-left:11%; margin-top: 1em">Copyright
© 2012-2017 gEDA Contributors. <br>
Copyright © 2017-2022 Lepton Developers. <br>
License GPLv2+: GNU GPL version 2 or later. Please see the
’COPYING’ <br>
file included with this program for full details.</p>
<p style="margin-left:11%; margin-top: 1em">This is free
software: you are free to change and redistribute it. <br>
There is NO WARRANTY, to the extent permitted by law.</p>
<h2>SEE ALSO
<a name="SEE ALSO"></a>
</h2>
<p style="margin-left:11%; margin-top: 1em"><b>lepton-schematic</b>(1),
<b>lepton-symcheck</b>(1), <b>pcb</b>(1),
<b>gnucap</b>(1)</p>
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