1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132
|
.TH "libnvme" 9 "enum nvme_cmbsz" "April 2025" "API Manual" LINUX
.SH NAME
enum nvme_cmbsz \- This field indicates the controller memory buffer size
.SH SYNOPSIS
enum nvme_cmbsz {
.br
.BI " NVME_CMBSZ_SQS_SHIFT"
,
.br
.br
.BI " NVME_CMBSZ_CQS_SHIFT"
,
.br
.br
.BI " NVME_CMBSZ_LISTS_SHIFT"
,
.br
.br
.BI " NVME_CMBSZ_RDS_SHIFT"
,
.br
.br
.BI " NVME_CMBSZ_WDS_SHIFT"
,
.br
.br
.BI " NVME_CMBSZ_SZU_SHIFT"
,
.br
.br
.BI " NVME_CMBSZ_SZ_SHIFT"
,
.br
.br
.BI " NVME_CMBSZ_SQS_MASK"
,
.br
.br
.BI " NVME_CMBSZ_CQS_MASK"
,
.br
.br
.BI " NVME_CMBSZ_LISTS_MASK"
,
.br
.br
.BI " NVME_CMBSZ_RDS_MASK"
,
.br
.br
.BI " NVME_CMBSZ_WDS_MASK"
,
.br
.br
.BI " NVME_CMBSZ_SZU_MASK"
,
.br
.br
.BI " NVME_CMBSZ_SZ_MASK"
,
.br
.br
.BI " NVME_CMBSZ_SZU_4K"
,
.br
.br
.BI " NVME_CMBSZ_SZU_64K"
,
.br
.br
.BI " NVME_CMBSZ_SZU_1M"
,
.br
.br
.BI " NVME_CMBSZ_SZU_16M"
,
.br
.br
.BI " NVME_CMBSZ_SZU_256M"
,
.br
.br
.BI " NVME_CMBSZ_SZU_4G"
,
.br
.br
.BI " NVME_CMBSZ_SZU_64G"
};
.SH Constants
.IP "NVME_CMBSZ_SQS_SHIFT" 12
Shift amount to get the submission queue support
.IP "NVME_CMBSZ_CQS_SHIFT" 12
Shift amount to get the completion queue support
.IP "NVME_CMBSZ_LISTS_SHIFT" 12
Shift amount to get the PLP SGL list support
.IP "NVME_CMBSZ_RDS_SHIFT" 12
Shift amount to get the read data support
.IP "NVME_CMBSZ_WDS_SHIFT" 12
Shift amount to get the write data support
.IP "NVME_CMBSZ_SZU_SHIFT" 12
Shift amount to get the size units
.IP "NVME_CMBSZ_SZ_SHIFT" 12
Shift amount to get the size
.IP "NVME_CMBSZ_SQS_MASK" 12
Mask to get the submission queue support
.IP "NVME_CMBSZ_CQS_MASK" 12
Mask to get the completion queue support
.IP "NVME_CMBSZ_LISTS_MASK" 12
Mask to get the PLP SGL list support
.IP "NVME_CMBSZ_RDS_MASK" 12
Mask to get the read data support
.IP "NVME_CMBSZ_WDS_MASK" 12
Mask to get the write data support
.IP "NVME_CMBSZ_SZU_MASK" 12
Mask to get the size units
.IP "NVME_CMBSZ_SZ_MASK" 12
Mask to get the size
.IP "NVME_CMBSZ_SZU_4K" 12
4 KiB
.IP "NVME_CMBSZ_SZU_64K" 12
64 KiB
.IP "NVME_CMBSZ_SZU_1M" 12
1 MiB
.IP "NVME_CMBSZ_SZU_16M" 12
16 MiB
.IP "NVME_CMBSZ_SZU_256M" 12
256 MiB
.IP "NVME_CMBSZ_SZU_4G" 12
4 GiB
.IP "NVME_CMBSZ_SZU_64G" 12
64 GiB
|