File: common_capability.c

package info (click to toggle)
libpciaccess 0.14-1
  • links: PTS, VCS
  • area: main
  • in suites: bullseye, buster, sid
  • size: 2,248 kB
  • sloc: ansic: 6,611; sh: 4,188; makefile: 79
file content (199 lines) | stat: -rw-r--r-- 5,611 bytes parent folder | download
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
/*
 * (C) Copyright IBM Corporation 2006
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * on the rights to use, copy, modify, merge, publish, distribute, sub
 * license, and/or sell copies of the Software, and to permit persons to whom
 * the Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.  IN NO EVENT SHALL
 * IBM AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

/**
 * \file common_capability.c
 * Platform independent PCI capability related routines.
 *
 * In addition to including the interface glue for \c pci_device_get_agp_info,
 * this file also contains a generic implementation of that function.
 *
 * \author Ian Romanick <idr@us.ibm.com>
 */
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif

#include <stdlib.h>
#include <stdio.h>
#include <errno.h>

#include "pciaccess.h"
#include "pciaccess_private.h"

/**
 * Generic implementation of \c pci_system_methods::fill_capabilities.
 *
 * \param dev   Device whose capability information is to be processed.
 *
 * \return
 * Zero on success or an errno value on failure.
 *
 * \todo
 * Once more than just the AGP capability is supported, the body of each of
 * the cases in the capability processing loop should probably be broken out
 * into its own function.
 *
 * \todo
 * Once more than just the AGP capability is supported, some care will need
 * to be taken in partial failure cases.  If, say, the first capability is
 * correctly processed but the second fails, the function would be re-called
 * later to try again for the second capability.  This could lead to memory
 * leaks or other quirky behavior.
 */
_pci_hidden int
pci_fill_capabilities_generic( struct pci_device * dev )
{
    struct pci_device_private * const dev_priv =
      (struct pci_device_private *) dev;
    int       err;
    uint16_t  status;
    uint8_t   cap_offset;


    err = pci_device_cfg_read_u16( dev, & status, 6 );
    if ( err ) {
	return err;
    }

    /* Are PCI capabilities supported by this device?
     */
    if ( (status & 0x0010) == 0 ) {
	return ENOSYS;
    }

    err = pci_device_cfg_read_u8( dev, & cap_offset, 52 );
    if ( err ) {
	return err;
    }


    /* Process each of the capabilities list in the PCI header.
     */
    while ( cap_offset != 0 ) {
	uint8_t cap_id;
	uint8_t next_cap;

	err = pci_device_cfg_read_u8( dev, & cap_id, cap_offset );
	if ( err ) {
	    return err;
	}

	err = pci_device_cfg_read_u8( dev, & next_cap, cap_offset + 1 );
	if ( err ) {
	    return err;
	}

	switch ( cap_id ) {
	case 2: {
	    struct pci_agp_info * agp_info;
	    uint32_t agp_status;
	    uint8_t agp_ver;


	    err = pci_device_cfg_read_u8( dev, & agp_ver, cap_offset + 2 );
	    if ( err ) {
		return err;
	    }

	    err = pci_device_cfg_read_u32( dev, & agp_status, cap_offset + 4 );
	    if ( err ) {
		return err;
	    }

	    agp_info = calloc( 1, sizeof( struct pci_agp_info ) );
	    if ( agp_info == NULL ) {
		return ENOMEM;
	    }

	    agp_info->config_offset = cap_offset;

	    agp_info->major_version = (agp_ver & 0x0f0) >> 4;
	    agp_info->minor_version = (agp_ver & 0x00f);

	    agp_info->rates = (agp_status & 0x07);

	    /* If AGP3 is supported, then the meaning of the rates values
	     * changes.
	     */
	    if ( (agp_status & 0x08) != 0 ) {
		agp_info->rates <<= 2;
	    }

	    /* Some devices, notably motherboard chipsets, have the AGP3
	     * capability set and the 4x bit set.  This results in an
	     * impossible 16x mode being listed as available.  I'm not 100%
	     * sure this is the right solution.
	     */
	    agp_info->rates &= 0x0f;


	    agp_info->fast_writes = (agp_status & 0x0010) != 0;
	    agp_info->addr64 =      (agp_status & 0x0020) != 0;
	    agp_info->htrans =      (agp_status & 0x0040) == 0;
	    agp_info->gart64 =      (agp_status & 0x0080) != 0;
	    agp_info->coherent =    (agp_status & 0x0100) != 0;
	    agp_info->sideband =    (agp_status & 0x0200) != 0;
	    agp_info->isochronus =  (agp_status & 0x10000) != 0;

	    agp_info->async_req_size = 4 + (1 << ((agp_status & 0xe000) >> 13));
	    agp_info->calibration_cycle_timing = ((agp_status & 0x1c00) >> 10);
	    agp_info->max_requests = 1 + ((agp_status & 0xff000000) >> 24);

	    dev_priv->agp = agp_info;
	    break;
	}

	/* No other capabilities are currently handled.
	 */
	default:
	    printf( "Unknown cap 0x%02x @ 0x%02x\n", cap_id, cap_offset );
	    break;
	}

	cap_offset = next_cap;
    }

    return 0;
}


/**
 * Get AGP capability data for a device.
 */
const struct pci_agp_info *
pci_device_get_agp_info( struct pci_device * dev )
{
    struct pci_device_private * dev_priv = (struct pci_device_private *) dev;

    if ( dev == NULL ) {
	return NULL;
    }

    if ( dev_priv->agp == NULL ) {
	(void) (*pci_sys->methods->fill_capabilities)( dev );
    }

    return dev_priv->agp;
}