File: 16_std.t

package info (click to toggle)
libverilog-perl 3.482-2
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid, trixie
  • size: 8,728 kB
  • sloc: perl: 8,685; yacc: 3,387; cpp: 2,266; lex: 1,502; makefile: 8; fortran: 3
file content (20 lines) | stat: -rwxr-xr-x 571 bytes parent folder | download
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
#!/usr/bin/perl -w
# DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package
#
# Copyright 2009-2024 by Wilson Snyder.  This program is free software;
# you can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

use strict;
use Test::More;

BEGIN { plan tests => 3 }
BEGIN { require "./t/test_utils.pl"; }

use Verilog::Std;
ok(1, "use");

like (Verilog::Std::std(), qr/endpackage/);

# Make sure data sticks around
like (Verilog::Std::std(), qr/endpackage/);