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root_module $root (
);
localparam GLOBAL_PARAM = 1; // Local Variables:
// eval:(verilog-read-defines)
// End:
endroot_module
module v_bug917 (
a, b, m);
input a; // a-First
output b; // b-Third
// Third
output m; // m-Second
endmodule
module v_bug917p (
a, b);
input a; // a-First
output b; // b-Secondparen
// Third
endmodule
module v_comments (
a, b, c, d, d1, d2, d3);
input a; // comment for a
inout [10:0] b;
output [0:10] c; // comment for c
output reg d;
output [32:0] d1;
output [(MATH-1):0] d2;
output [32-1:0] d3;
var reg [11:0] e; // Comment for e
endmodule
module v_hier_noport (
);
parameter P;
var reg internal;
endmodule
module v_hier_sub (
avec, clk, qvec);
parameter FROM_DEFPARAM = 1;
genvar K;
genvar K_UNUSED;
supply1 a1; // Outputs
input [3:0] avec; // Comment for v_hier_sub, avec
input clk;
output [3:0] qvec; /* Comment for v_hier_sub, qvec */
v_hier_subsub #(.IGNORED('sh20)) subsub0 (.a(a1), .q(qvec[0]));
v_hier_subsub subsub2 (.a(1'b0), .q(qvec[2]));
endmodule
module v_hier_subsub (
a, q);
parameter IGNORED = 0;
input signed a;
output q; // Test protected
//"
endmodule
module v_hier_top (
clk);
localparam [0:0] WC_p1 = 0;
localparam [2:0] WC_p3 = 0;
localparam WC_p32 = 0;
localparam [-1:2] WC_p4 = 0;
localparam integer WC_pint = 0; // Assignments
wire WC_w1;
wire [0:0] WC_w1b;
wire [2:0] WC_w3;
wire [-1:2] WC_w4;
wire asn_clk;
input clk; /* pragma jsc_clk */
missing missing ();
v_recursive #(.DEPTH(3)) recursive ();
v_hier_sub sub (.avec({avec[3],avec[2:0]}), .clk(1'b0), .qvec(qvec[3:0]));
defparam sub.FROM_DEFPARAM = 2;
assign asn_clk = clk;
endmodule
module v_hier_top2 (
clk, iosig);
input clk;
inout [2:0] iosig; /* synthesis useioff = 1 //*synthesis fpga_attr = "BLAH=ON"//* synthesis fpga_pin = "A22"*/
/* synthesis aftersemi*/
// NetListName=F12_IO
v_hier_noport noport ();
v_hier_noport #(.P(1)) noporta [1:0] ();
v_hier_noport #(.P(1)) noportp ();
endmodule
module v_recursive (
);
parameter DEPTH = 1;
v_recursive #(.DEPTH(DEPTH-1)) recurse ();
endmodule
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