File: 42_dumpcheck_2v.out

package info (click to toggle)
libverilog-perl 3.482-2
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid, trixie
  • size: 8,728 kB
  • sloc: perl: 8,685; yacc: 3,387; cpp: 2,266; lex: 1,502; makefile: 8; fortran: 3
file content (36 lines) | stat: -rw-r--r-- 674 bytes parent folder | download | duplicates (7)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
module bug278 (
   iow, iw, ow);
   inout iow;
   input iw;
   output ow;
endmodule

module foo (
   abcconst, def, noconnect, x, y);
   input [2:0] abcconst;
   input [31:0] def;
   input signed [3:0] noconnect;
   input x;
   input y;
endmodule

module foo2 (
   x, y, z);
   output reg x;
   input y;
   input z;
endmodule

module pinorder4 (
   );
   wire [31:0] IPCD_const = 32'h1;
   wire [7:0] a_i;
   wire b_i;
   wire d_o;
   foo foo1 (.abcconst(3'h0), .def(IPCD_const), .noconnect(), .x(a_i), .y(b_i));
   foo2 foo2 (.x(b_i), .y(d_o), .z(a_i[0]));
   foo foo3 (.abcconst(3'h0), .def(IPCD_const), .x(a_i), .y(b_i));
   assign a_i = 0;
   assign b_i = 0;
endmodule