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<vhier>
<cells>
<cell name="v_hier_top" submodname="v_hier_top" hier="v_hier_top" filename="verilog/v_hier_top.v">
<cell name="recursive" submodname="v_recursive" hier="v_hier_top.recursive" filename="verilog/v_recursive.v">
</cell>
<cell name="sub" submodname="v_hier_sub" hier="v_hier_top.sub" filename="verilog/v_hier_sub.v">
<cell name="subsub0" submodname="v_hier_subsub" hier="v_hier_top.sub.subsub0" filename="verilog/v_hier_subsub.v">
</cell>
<cell name="subsub2" submodname="v_hier_subsub" hier="v_hier_top.sub.subsub2" filename="verilog/v_hier_subsub.v">
</cell>
</cell>
</cell>
</cells>
<module_files>
<file>verilog/v_hier_top.v</file>
<file>verilog/v_hier_sub.v</file>
<file>verilog/v_recursive.v</file>
<file>verilog/v_hier_subsub.v</file>
</module_files>
<input_files>
<file>verilog/v_hier_inc.vh</file>
<file>verilog/v_hier_sub.v</file>
<file>verilog/v_hier_subsub.v</file>
<file>verilog/v_hier_top.v</file>
<file>verilog/v_recursive.v</file>
</input_files>
<includes>
<file name="verilog/v_hier_top.v">
<inc name="verilog/v_hier_inc.vh" />
</file>
</includes>
<missing_modules>
<module name="missing" />
</missing_modules>
</vhier>
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