1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
|
/* This file contains some instantiations of an unknown module that use bit vectors. */
module top(i,o);
input [31:0] i;
output [31:0] o;
wire [3:0] somebus, someotherbus;
wire somenet_1,somenet_2,somenet_3;
wire [29:0] somewidebus;
parameter SOMEPARAM = 10;
assign somewidebus=i[31:2];
assign o[1]=somenet_1;
assign o[2]=somenet_2;
assign o[0]=1'b0;
assign o[3]=someotherbus[2];
assign o[28:4]=25'b0;
assign o[31]=~somenet_1;
mod instmod_1 (
.a(somebus),
.y(somenet_1)
);
mod instmod_2 (
.a(somebus),
.y(someotherbus[2])
);
mod instmod_3 (
.a(somewidebus[24:21]),
.y(somenet_2)
);
mod instmod_4 (
.a(i[31:27]),
.y(o[29])
);
mod instmod_5 (
.a({somenet_1,3'b101,someotherbus[2],somewidebus[2:1]}),
.y(o[30])
);
mod instmod_6 (
.a({somenet_1,3'b101,{someotherbus[2],someotherbus[2]},somewidebus[2:1]}),
.y(o[30])
);
mod instmod_7 (
.a(somebus[{SOMEPARAM_3[1],SOMEPARAM_3[0]}]),
.y(someotherbus[2])
);
endmodule
|
