1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
|
; - - memory
; 0 1 2 3 4 5 6 7 8 9 a b c d e f
00001000: 00 08 00 09 00 0a 00 0b 00 0c 00 0d 00 0e 00 90
00001010: 00 0f 00 68 40 00 69 40 00 6a 40 00 6b 40 00 6c
00001020: 40 00 6d 40 00 6e 40 00 6f 40 26 00 90 00 08 26
00001030: 00 91 00 08 26 00 92 00 08 26 00 93 00 08 26 00
00001040: 94 00 08 26 00 95 00 08 26 00 96 00 08 26 00 97
00001050: 00 08 00 f0 00 f1 00 f2 00 f3 00 f4 00 f5 00 f6
00001060: 00 f7 67 00 01 f4
00020000: *55
00020030: *66
00020040: *66
00024ff0: *55
00025000: *aa
00025030: *66
00025040: *cc
00029000: *55
0002aa90: *44
0002fff0: *55
00049ff0: *55
0004a000: *55
0004a030: *66
0004a040: *cc
000607f0: *33
00060800: *33
000657f0: *33
00065800: *66
0006a7f0: *33
0006a800: *66
; - - registers
msr[0010] 0000000000000022 ; tsc
cr0=00000000 cr1=00000000 cr2=00000000 cr3=00000000 cr4=00000000
dr0=00000000 dr1=00000000 dr2=00000000 dr3=00000000 dr6=00000000 dr7=00000000
gdt.base=00000000 gdt.limit=ffff
idt.base=00000000 idt.limit=ffff
tr=0000 tr.base=00000000 tr.limit=00000000 tr.acc=0000
ldt=0000 ldt.base=00000000 ldt.limit=00000000 ldt.acc=0000
cs=0100 cs.base=00001000 cs.limit=0000ffff cs.acc=009b
ss=4000 ss.base=00040000 ss.limit=0000ffff ss.acc=0093
ds=2000 ds.base=00020000 ds.limit=0000ffff ds.acc=0093
es=6000 es.base=00060000 es.limit=0000ffff es.acc=0093
fs=0000 fs.base=00000000 fs.limit=0000ffff fs.acc=0093
gs=0000 gs.base=00000000 gs.limit=0000ffff gs.acc=0093
eax=00004444 ebx=0000d844 ecx=0000aa99 edx=00008877
esi=00000000 edi=0000ffff ebp=0000a000 esp=00000000
eip=00000066 eflags=00000006 ; pf
|